Unpack and zeroextend multivector elements
Unpack elements from one or two source vectors and then zeroextend them to place in elements of twice their size within the two or four destination vectors.
This instruction is unpredicated.
It has encodings from 2 classes: Two registers and Four registers
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  0  0  0  0  0  1  size  1  0  0  1  0  1  1  1  1  0  0  0  Zn  Zd  1  
U 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd:'0'); constant integer nreg = 2; constant boolean unsigned = TRUE;
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1  1  0  0  0  0  0  1  size  1  1  0  1  0  1  1  1  1  0  0  0  Zn  0  Zd  0  1  
U 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd:'00'); constant integer nreg = 4; constant boolean unsigned = TRUE;
<T> 
Is the size specifier,
encoded in

<Zd4> 
Is the name of the fourth scalable vector register of the destination multivector group, encoded as "Zd" times 4 plus 3. 
<Zn1> 
Is the name of the first scalable vector register of the source multivector group, encoded as "Zn" times 2. 
<Zd2> 
Is the name of the second scalable vector register of the destination multivector group, encoded as "Zd" times 2 plus 1. 
<Zn> 
Is the name of the source scalable vector register, encoded in the "Zn" field. 
<Tb> 
Is the size specifier,
encoded in

<Zn2> 
Is the name of the second scalable vector register of the source multivector group, encoded as "Zn" times 2 plus 1. 
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer hsize = esize DIV 2; constant integer sreg = nreg DIV 2; array [0..3] of bits(VL) results; for r = 0 to sreg1 constant bits(VL) operand = Z[n+r, VL]; for i = 0 to 1 for e = 0 to elements1 constant bits(hsize) element = Elem[operand, i*elements + e, hsize]; Elem[results[2*r+i], e, esize] = Extend(element, esize, unsigned); for r = 0 to nreg1 Z[d+r, VL] = results[r];
If PSTATE.DIT is 1:
Internal version only: aarchmrs v202403_relA, pseudocode v202403_rel, sve v202403_rel ; Build timestamp: 20240326T09:45
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