Floatingpoint Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floatingpoint values in the SIMD&FP source register to integral floatingpoint values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.
A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
A floatingpoint exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floatingpoint exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Halfprecision and Singleprecision and doubleprecision
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
0  Q  0  0  1  1  1  0  0  1  1  1  1  0  0  1  1  0  0  0  1  0  Rn  Rd  
U  o2  o1 
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean exact = FALSE; FPRounding rounding; case U:o1:o2 of when '0xx' rounding = FPDecodeRounding(o1:o2); when '100' rounding = FPRounding_TIEAWAY; when '101' UNDEFINED; when '110' rounding = FPRoundingMode(FPCR); exact = TRUE; when '111' rounding = FPRoundingMode(FPCR);
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
0  Q  0  0  1  1  1  0  0  sz  1  0  0  0  0  1  1  0  0  0  1  0  Rn  Rd  
U  o2  o1 
integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean exact = FALSE; FPRounding rounding; case U:o1:o2 of when '0xx' rounding = FPDecodeRounding(o1:o2); when '100' rounding = FPRounding_TIEAWAY; when '101' UNDEFINED; when '110' rounding = FPRoundingMode(FPCR); exact = TRUE; when '111' rounding = FPRoundingMode(FPCR);
<Vd> 
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. 
<T> 
For the halfprecision variant: is an arrangement specifier,
encoded in
 
For the singleprecision and doubleprecision variant: is an arrangement specifier,
encoded in

<Vn> 
Is the name of the SIMD&FP source register, encoded in the "Rn" field. 
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; bits(esize) element; for e = 0 to elements1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact); V[d, datasize] = result;
Internal version only: aarchmrs v202403_relA, pseudocode v202403_rel, sve v202403_rel ; Build timestamp: 20240326T09:45
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