Multivector floatingpoint minimum number
Determine the minimum number value of floatingpoint elements of the two or four second source vectors and the corresponding floatingpoint elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors.
Regardless of the value of FPCR.AH, the behavior is as follows:
This instruction follows SME2 floatingpoint numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.
This instruction is unpredicated.
It has encodings from 2 classes: Two registers and Four registers
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  0  0  0  0  0  1  != 00  1  Zm  0  1  0  1  1  0  0  0  1  0  0  1  Zdn  1  
size 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer dn = UInt(Zdn:'0'); constant integer m = UInt(Zm:'0'); constant integer nreg = 2;
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  0  0  0  0  0  1  != 00  1  Zm  0  0  1  0  1  1  1  0  0  1  0  0  1  Zdn  0  1  
size 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer dn = UInt(Zdn:'00'); constant integer m = UInt(Zm:'00'); constant integer nreg = 4;
<T> 
Is the size specifier,
encoded in

<Zdn4> 
Is the name of the fourth scalable vector register of the destination and first source multivector group, encoded as "Zdn" times 4 plus 3. 
<Zdn2> 
Is the name of the second scalable vector register of the destination and first source multivector group, encoded as "Zdn" times 2 plus 1. 
<Zm4> 
Is the name of the fourth scalable vector register of the second source multivector group, encoded as "Zm" times 4 plus 3. 
<Zm2> 
Is the name of the second scalable vector register of the second source multivector group, encoded as "Zm" times 2 plus 1. 
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; array [0..3] of bits(VL) results; for r = 0 to nreg1 constant bits(VL) operand1 = Z[dn+r, VL]; constant bits(VL) operand2 = Z[m+r, VL]; for e = 0 to elements1 constant bits(esize) element1 = Elem[operand1, e, esize]; constant bits(esize) element2 = Elem[operand2, e, esize]; Elem[results[r], e, esize] = FPMinNum(element1, element2, FPCR); for r = 0 to nreg1 Z[dn+r, VL] = results[r];
Internal version only: aarchmrs v202403_relA, pseudocode v202403_rel, sve v202403_rel ; Build timestamp: 20240326T09:45
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