Add multivector to multivector with ZA array vector results
Add all corresponding elements of the two or four second source vectors and first source vectors and place the results in the corresponding elements of the ZA singlevector groups.
The singlevector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA singlevector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 64bit integer variant is implemented.
It has encodings from 2 classes: Two ZA singlevectors and Four ZA singlevectors
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  0  0  0  0  0  1  1  sz  1  Zm  0  0  Rv  1  1  0  Zn  0  1  0  off3  
S 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 32 << UInt(sz); constant integer n = UInt(Zn:'0'); constant integer m = UInt(Zm:'0'); constant integer offset = UInt(off3); constant integer nreg = 2;
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  0  0  0  0  0  1  1  sz  1  Zm  0  1  0  Rv  1  1  0  Zn  0  0  1  0  off3  
S 
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer esize = 32 << UInt(sz); constant integer n = UInt(Zn:'00'); constant integer m = UInt(Zm:'00'); constant integer offset = UInt(off3); constant integer nreg = 4;
<T> 
Is the size specifier,
encoded in

<Wv> 
Is the 32bit name of the vector select register W8W11, encoded in the "Rv" field. 
<offs> 
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. 
<Zn4> 
Is the name of the fourth scalable vector register of the first source multivector group, encoded as "Zn" times 4 plus 3. 
<Zn2> 
Is the name of the second scalable vector register of the first source multivector group, encoded as "Zn" times 2 plus 1. 
<Zm4> 
Is the name of the fourth scalable vector register of the second source multivector group, encoded as "Zm" times 4 plus 3. 
<Zm2> 
Is the name of the second scalable vector register of the second source multivector group, encoded as "Zm" times 2 plus 1. 
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV nreg; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; for r = 0 to nreg1 constant bits(VL) operand1 = Z[n+r, VL]; constant bits(VL) operand2 = Z[m+r, VL]; for e = 0 to elements1 constant bits(esize) element1 = Elem[operand1, e, esize]; constant bits(esize) element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = element1 + element2; ZAvector[vec, VL] = result; vec = vec + vstride;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v202403_relA, pseudocode v202403_rel, sve v202403_rel ; Build timestamp: 20240326T09:45
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