I have moved the basic use and set-up of the device to the corresponding OpenWrt ITian SQ201 page where it is properly maintained by the community. This page is just my own musings and tricks, and a bit of history.
This is a pretty funny gemini-based router and NAS. All references on the Internet (almost) are in polish, but the FCC documentation seems to come from people in Taiwan. So it seems like a polish company partnered with a Taiwanese electronics producer to make a home router and NAS for the polish market, using the Gemini SL3516 chip. ITian has not been heard from for the last ten years or so.
- A tested zImage based on kernel v4.20-rc1 with the SQ201 device tree attached - this will attempt to boot from flash partition /dev/mtdblock2 which should contain an OpenWRT root filesystem on squashfs+JFFS2 overlay format.
- A tested zImage based on kernel v4.17-rc3 with the SQ201 device tree and initramfs attached.
- A tested zImage based on kernel v4.13-rc3 with the SQ201 device tree and initramfs attached.
- A tested zImage based on kernel v4.11-rc1 with the SQ201 device tree and initramfs attached.
- A tested zImage based on kernel v4.10-rc2 with the SQ201 device tree and initramfs attached.
SQ201-Specifics: Getting SQ201 RT2561s wireless going
- Enable the SQ201 PCI devices:
- 0000:00:00.0 0x159b/0x4321 Faraday root hub?
- 0000:00:09.0 0x1106/0x3038 VIA Technologies, Inc. VT82xx/62xx UHCI USB 1.1 Controller
- 0000:00:09.1 0x1106/0x3038 VIA Technologies, Inc. VT82xx/62xx UHCI USB 1.1 Controller
- 0000:00:09.2 0x1106/0x3104 VIA Technologies, Inc. USB 2.0 EHCI Controller
- 0000:00:0c.0 0x1814/0x0301 RaLink RT2561/RT61 802.11g PCI
- Get rt2561s.bin from the Linux firmware repository, build and package into your rootfs, it needs to land in /lib/firmware/rt2561s.bin
- ifconfig wlan0 192.168.1.64 netmask 255.255.255.0 up
Analyzing the Firmware
Log into the vendor-supplied firmware with admin/admin.
cat /proc/interrupts CPU0 1: 0 eth1 2: 21 eth0 4: 116 ide1 8: 0 sl2312 pci int 15: 35981 SL2312 Timer Tick 18: 2118 sl2312 22: 0 GPIO1 23: 0 GPIO2 25: 0 cir 64: 0 uhci_hcd:usb2 65: 0 uhci_hcd:usb3 66: 0 ehci_hcd:usb1 67: 7350 ra0 Err: 0 cat /proc/iomem 00000000-07ffffff : System RAM 00025000-0033e5d3 : Kernel text 00340000-004759bf : Kernel data 42000000-4200004f : serial_sl2312 58000000-58007fff : 0000:00:0c.0 58008000-580080ff : ehci_hcd 63000000-63000040 : lepus-sata0 63400000-63400040 : lepus-sata 68000000-68000fff : ehci-hcd-FOTG2XX 69000000-69000fff : ehci-hcd-FOTG2XX-1 f4800000-f4800038 : irq_handler cd /sys/bus/platform/devices && ls -al lrwxrwxrwx 1 root root 0 Dec 31 16:09 lepus-sata -> ../../../devices/platform/lepus-sata lrwxrwxrwx 1 root root 0 Dec 31 16:09 lepus-sata0 -> ../../../devices/platform/lepus-sata0 lrwxrwxrwx 1 root root 0 Dec 31 16:09 ehci-hcd-FOTG2XX -> ../../../devices/platform/ehci-hcd-FOTG2XX lrwxrwxrwx 1 root root 0 Dec 31 16:09 ehci-hcd-FOTG2XX-1 -> ../../../devices/platform/ehci-hcd-FOTG2XX-1 cd /sys/bus/usb/devices && ls -al lrwxrwxrwx 1 root root 0 Dec 31 16:11 usb1 -> ../../../devices/pci0000:00/0000:00:09.2/usb1 lrwxrwxrwx 1 root root 0 Dec 31 16:11 1-0:1.0 -> ../../../devices/pci0000:00/0000:00:09.2/usb1/1-0:1.0 lrwxrwxrwx 1 root root 0 Dec 31 16:11 usb2 -> ../../../devices/pci0000:00/0000:00:09.0/usb2 lrwxrwxrwx 1 root root 0 Dec 31 16:11 2-0:1.0 -> ../../../devices/pci0000:00/0000:00:09.0/usb2/2-0:1.0 lrwxrwxrwx 1 root root 0 Dec 31 16:11 usb3 -> ../../../devices/pci0000:00/0000:00:09.1/usb3 lrwxrwxrwx 1 root root 0 Dec 31 16:11 3-0:1.0 -> ../../../devices/pci0000:00/0000:00:09.1/usb3/3-0:1.0
Source code from other vendors suggest things like this for the MDIO GPIO pins to talk to the Vitesse switch and the PHY searching for the keyword VITESSE_G5SWITCH:
- If bit 30 in GMAC_GLOBAL_BASE_ADDR+0x04 is set, and we are on the C3 ASIC, GMAC_GLOBAL_BASE_ADDR+0x0 == 0x3516C3, then bit 4 in GMAC_GLOBAL_BASE_ADDR+0x30 is inverted.
- SPI is then used to read something
- Then bit 4 in GMAC_GLOBAL_BASE_ADDR+0x30 is set to 1
- ethernet 1 is used for the switch
- sl_switch.c contains some logic to talk to switches
- Two SPI ports elegible:
First (all on gpio1 at 0x4e000000 so offset on this controller):
- CS: GPIO 31
- MISO: GPIO 30
- MOSI: GPIO 29
- CK: GPIO 28
- CS: GPIO 9
- MISO: GPIO 10
- MOSI: GPIO 7
- CK: GPIO 5
Add a proper device tree for the device Update the SQ201 device tree for connecting the first ethernet interface to the Marvell 88E1111 PHY chip (patch merged for v4.19)
- Update the Gemini defconfig with the Marvell PHY
Create a new DSA driver for the Vitesse VSC7385/VSC7395 router chip, OpenWRT has a firmware loading hack since ages Create a device tree binding for the Vitesse VSC73xx switches (patch merged for v4.19) Extend the Vitesse PHY driver to handle the odd VSC73xx switches (patch merged for v4.19) Create a DSA driver for the Vitesse VSC73xx switches (patch merged for v4.19) Update the SQ201 device tree for connecting the second ethernet interface to the VSC7395 chip using a fixed link (patch merged for v4.19)
- Update the Gemini defconfig with the VSC73xx driver
Create a pin control flash add-on so we can multiplex NOR flash and GPIO access for the LEDs.
Fix installation procedure and flash layout.
Bring up interfaces:
ifconfig eth0 192.168.1.2 netmask 255.255.255.0 up ifconfig eth1 169.254.1.2 netmask 255.255.255.0 up ifconfig lan1 up
ifconfig lan1 mtu 9000 ifconfig eth1 mtu 9000 ifconfig eth0 mtu 9000 ping -s 8000 <ip>