PAL16R8 PAT8040 **-5173-** MK, 85-02-19 DS60 4680 I/O BACKPLANE CONTROL CLK ACK PHB PHA FCK A06 A04 DIR CYC GND OE DBE LA6 STB CSB EXP CSS TRE DTA VCC ;EQUATIONS: /DBE := DBE*/CYC* ACK* FCK* PHB* PHA + DBE*/CYC*/ACK* FCK*/PHB*/PHA + /DBE*/CYC /LA6 := LA6*/CYC* ACK* FCK*/CSS*/A06 + /LA6*/CYC* DBE + /LA6*/CYC*/FCK + LA6*/CYC*/DBE* FCK* PHB + /LA6*/CYC*/DBE*/STB + /LA6*/CYC*/DBE*/CSB + /LA6*/CYC*/DBE*/EXP + /LA6*/CYC*/DBE*/TRE /STB := STB*/CYC* ACK* FCK*/DBE*/LA6* DTA* CSB* EXP + STB*/CYC* ACK* FCK*/DBE*/DIR* DTA + /STB*/CYC*/FCK + /STB*/CYC* DTA + /STB*/CYC*/DTA* DIR*/PHB*/PHA /CSB := CSB*/CYC* ACK* FCK*/DBE* LA6*/A04* DTA* DIR* STB* EXP + /CSB*/CYC*/FCK + /CSB*/CYC* DTA + /CSB*/CYC*/DTA* DIR*/PHB*/PHA /EXP := EXP*/CYC* ACK* FCK*/DBE* LA6* A04* DTA* DIR* STB* CSB + /EXP*/CYC*/FCK + /EXP*/CYC* DTA + /EXP*/CYC*/DTA* DIR*/PHB*/PHA /CSS := CSS*/CYC* ACK* FCK* DBE*/PHB*/PHA + /CSS*/CYC*/FCK + /CSS*/CYC*/PHB* PHA /TRE := TRE*/CYC*/ACK* FCK* DBE*/PHB*/PHA + /TRE*/CYC*/FCK + /TRE*/CYC* DTA + /TRE*/CYC*/DTA* DIR*/PHB*/PHA /DTA := DTA*/CYC* FCK*/DBE*/LA6* DIR* PHB* PHA + DTA*/CYC* FCK*/DBE*/LA6*/DIR*/PHB*/PHA*/STB + DTA*/CYC* FCK*/DBE*/LA6*/DIR*/PHB*/PHA*/TRE + /DTA*/CYC*/FCK + /DTA*/CYC* DIR*/PHB*/PHA + /DTA*/CYC*/DIR*/PHB* PHA FUNCTION TABLE: CLK OE CYC ACK DIR A06 A04 PHB PHA FCK CSS LA6 DBE STB CSB EXP TRE DTA ;C C AD AA PP F CLD SCET D ;LOY CI 00 HH C SAB TSXR T ;KEC KR 64 BA K S6E BBPE A ----------------------------- CLH XX XX LL H XXX XXXX X ;1 INITIALIZE CLH XX XX LL L HHH HHHH H CHH XX XX LL H ZZZ ZZZZ Z ;----------------------------; READ OPERATION CLL HH LX LL L HHH HHHH H CLL HH LX LL H LHH HHHH H ;5 CLL HH LX LH L LHH HHHH H CLL HH LX LH H LLH HHHH H CLL HH LX HL L LLH HHHH H CLL HH XX HL H HLH HHHH H CLL HH XX HH L HLH HHHH H ;10 CLL HH XX HH H HLL HHHH H CLL HH XX LL L HLL HHHH H CLL HH XX LL H HHL LHHH H CLL HH XX LH L HHL LHHH H CLL HH XX LH H HHL LHHH H ;15 CLL HH XX HL L HHL LHHH H CLL HH XX HL H HLL LHHH H CLL HH XX HH L HLL LHHH H CLL HH XX HH H HLL LHHH L CLL HH XX LL L HLL LHHH L ;20 CLL HH XX LL H HLL LHHH L CLL HH XX LH L HLL LHHH L CLL HH XX LH H HLL HHHH H CLL HH XX HH L HLL HHHH H CLH HH XX HH H HHH HHHH H ;25 ;----------------------------; WRITE OPERATION CLL HL XX LL L HHH HHHH H CLL HL XX LL H LHH HHHH H CLL HL XX LH L LHH HHHH H CLL HL XX LH H LXH HHHH H CLL HL XX HL L LXH HHHH H ;30 CLL HL XX HL H HXH HHHH H CLL HL XX HH L HXH HHHH H CLL HL XX HH H HXL HHHH H CLL HL XX LL L HXL HHHH H CLL HL XX LL H HHL LHHH H ;35 CLL HL XX LH L HHL LHHH H CLL HL XX LH H HHL LHHH H CLL HL XX HL L HHL LHHH H CLL HL XX HL H HLL LHHH H CLL HL XX HH L HLL LHHH H ;40 CLL HL XX HH H HLL LHHH H CLL HL XX LL L HLL LHHH H CLL HL XX LL H HLL LHHH L CLL HL XX LH L HLL LHHH L CLL HL XX LH H HLL HHHH L ;45 CLL HL XX HL L HLL HHHH L CLL HL XX HL H HHL HHHH H CLH HL XX HH L HHH HHHH H ;----------------------------; DMA READ CYCLE CLL LH XX LL H HHL HHHL H CLL LH XX LH L HHL HHHL H ;50 CLL LH XX LH H HHL HHHL H CLL LH XX HL L HHL HHHL H CLL LH XX HL H HLL HHHL H CLL LH XX HH L HLL HHHL H CLL LH XX HH H HLL HHHL L ;55 CLL LH XX LL L HLL HHHL L CLL LH XX LL H HLL HHHL L CLL LH XX LH L HLL HHHL L CLL LH XX LH H HLL HHHH H CLL LH XX HL L HLL HHHH H ;60 CLH XX XX XX H HHH HHHH H ;----------------------------; DMA WRITE CYCLE CLL LL XX LL L HHH HHHH H CLL LL XX LL H HHL HHHL H CLL LL XX LH L HHL HHHL H CLL LL XX LH H HHL HHHL H ;65 CLL LL XX HL L HHL HHHL H CLL LL XX HL H HLL HHHL H CLL LL XX HH L HLL HHHL H CLL LL XX HH H HLL HHHL H CLL LL XX LL L HLL HHHL H ;70 CLL LL XX LL H HLL HHHL L CLL LL XX LH L HLL HHHL L CLL LL XX LH H HLL HHHH L CLL LL XX HL L HLL HHHH L CLL LL XX HL H HHL HHHH H ;75 CLH XX XX XX L HHH HHHH H ;----------------------------; CSB CYCLE CLL HH HL LL L HHH HHHH H CLL HH HL LL H LHH HHHH H CLL HH HL LH L LHH HHHH H CLL HH HL LH H LHH HHHH H ;80 CLL HH HL HL L LHH HHHH H CLL HH HL HL H HHH HHHH H CLL HH HL HH L HHH HHHH H CLL HH HL HH H HHL HHHH H CLL HH HL LL L HHL HHHH H ;85 CLL HH HL LL H HHL HLHH H CLL HH HL LH L HHL HLHH H CLL HH HL LH H HHL HLHH H CLL HH HL HL L HHL HLHH H CLL HH HL HL H HLL HLHH H ;90 CLL HH HL HH L HLL HLHH H CLL HH HL HH H HLL HLHH L CLL HH HL LL L HLL HLHH L CLL HH HL LL H HLL HLHH L CLL HH HL LH L HLL HLHH L ;95 CLL HH HL LH H HLL HHHH H CLL HH HL HH L HLL HHHH H CLH HH HL HH H HHH HHHH H ;----------------------------; EXP CYCLE CLL HH HH LL H LHH HHHH H CLL HH HH LH L LHH HHHH H ;100 CLL HH HH LH H LHH HHHH H CLL HH HH HL L LHH HHHH H CLL HH HH HL H HHH HHHH H CLL HH HH HH L HHH HHHH H CLL HH HH HH H HHL HHHH H ;105 CLL HH HH LL L HHL HHHH H CLL HH HH LL H HHL HHLH H CLL HH HH LH L HHL HHLH H CLL HH HH LH H HHL HHLH H CLL HH HH HL L HHL HHLH H ;110 CLL HH HH HL H HLL HHLH H CLL HH HH HH L HLL HHLH H CLL HH HH HH H HLL HHLH L CLL HH HH LL L HLL HHLH L CLL HH HH LL H HLL HHLH L ;115 CLL HH HH LH L HLL HHLH L CLL HH HH LH H HLL HHHH H CLL HH HH HH L HLL HHHH H CLH HH HL HH H HHH HHHH H ----------------------------- DESCRIPTION: THIS DEVICE GENERATES APPROPRIATE STROBE AND GATE TIMING FOR DS60 4680 I/O INTERFACE INPUT SIGNALS: ACK - HD68450 CHANNEL 2 CYCLE ACTIVE LOW PHB - TIMING GENERATOR PHASE B PHA - " " " A FCK - CPU CLOCK A06 - ADDRESS BIT 6 A04 - ADDRESS BIT 4 DIR - DIRECTION WRITE " " CYC - 4680 CYCLE " " OUTPUT SIGNALS: DBE - DATA BUS ENABLE " " LA6 - LATCHED ADDRESS 6 STB - INPUT/OUTPUT STROBE " " CSB - CSB READ STROBE " " EXP - I/O EXPANDER READ STROBE " " CSS - CHANNEL SELECT STROBE " " TRE - DMA TRANSFER ENABLE STROBE " " DTA - DATA ACKNOWLEDGE RESPONSE " "