PAL16R6 PAT8036 **-1110-** MK,85-04-18 DS60 RAM CONTROL SEQUENCER CLK ECK FAS SEF ERR RAM LDS UDS DIR GND OE CFE LLE ULE ES0 CAS HLD ES1 MS1 VCC ;EQUATIONS: /LLE:=/RAM*/FAS* ERR*/CAS*/ECK* DIR* ES0 + ;READ - ASSERT AFTER CAS /RAM*/FAS* ERR*/CAS*/ECK*/DIR* ES0*/UDS + ;BYTE WR - AFTER CAS IF /UDS /RAM*/FAS* ERR*/ES1*/ES0* CFE* DIR + ;EDC MODE - AT CORR. /RAM*/FAS* ERR*/ES1*/ES0* CFE*/DIR*/UDS + ;EDC MODE - WR. BYTE /RAM*/FAS* ERR*/LLE*/ES0 + ;KEEP TO END OF WRITE /RAM*/FAS* ERR*/LLE* ES1* ES0*/UDS + ;KEEP TO END OF CYCLE /RAM*/FAS* ERR*/LLE* ES1* ES0*/LDS ; " " " /ULE:=/RAM*/FAS* ERR*/CAS*/ECK* DIR* ES0 + ;READ - ASSERT AFTER CAS /RAM*/FAS* ERR*/CAS*/ECK*/DIR* ES0*/LDS + ;BYTE WR - AFTER CAS IF /LDS /RAM*/FAS* ERR*/ES1*/ES0* CFE* DIR + ;EDC MODE - AT CORR. /RAM*/FAS* ERR*/ES1*/ES0* CFE*/DIR*/LDS + ;EDC MODE - WR. BYTE /RAM*/FAS* ERR*/ULE*/ES0 + ;KEEP TO END OF WRITE /RAM*/FAS* ERR*/ULE* ES1* ES0*/UDS + ;KEEP TO END OF CYCLE /RAM*/FAS* ERR*/ULE* ES1* ES0*/LDS ; " " " /CAS:=/RAM*/FAS* ERR* CAS* ES1* ULE* LLE*/UDS*/ECK* DIR + ;READ /RAM*/FAS* ERR* CAS* ES1* ULE* LLE*/LDS*/ECK* DIR + ; " /RAM*/FAS* ERR* CAS* ES1* ULE* LLE*/UDS*/ECK*/DIR*/ES0 + ;WRITE OR PRERD /RAM*/FAS* ERR* CAS* ES1* ULE* LLE*/LDS*/ECK*/DIR*/ES0 + ; " /RAM*/FAS* ERR* CAS* ES1*/ES0*/HLD*/ECK + ;BYTE WR. OR CORR. /CAS* ECK ;KEEP ONE CYCLE /ES0:=/RAM*/FAS* ERR*/DIR* ULE* LLE* ES0*/ECK* CAS + ;WR - START /RAM*/FAS* ERR*/DIR* ULE* LLE* UDS* LDS*/ECK* CAS + ;WAIT FOR DATA STROBES /RAM*/FAS* ERR*/DIR* ULE* LLE*/UDS*/LDS*/ECK* CAS + ;WR WORD - CONTINUE /RAM*/FAS* ERR*/ES0* ECK + ;KEEP ONE CLOCK /RAM*/FAS* ERR*/ULE*/HLD*/ECK + ;BYTE WR OR CORRECTION /RAM*/FAS* ERR*/LLE*/HLD*/ECK + ; " " /RAM*/FAS* ERR*/ES1* CFE ;DETECTION /HLD:=/RAM*/FAS* ERR*/DIR*/ES0*/ECK*/UDS* LDS* ULE* LLE* HLD + ;BYTE WRITE /RAM*/FAS* ERR*/DIR*/ES0*/ECK* UDS*/LDS* ULE* LLE* HLD + ; " " /RAM*/FAS* ERR*/SEF* HLD*/ES1*/ECK + ;CORRECTABLE ERROR /RAM*/FAS* ERR*/HLD* ECK + ;KEEP ONE CLOCK /RAM*/FAS* ERR*/HLD*/DIR* ES0 + ;EXTEND AT BYTE WRITE /RAM*/FAS* ERR*/HLD*/DIR*/ES1 ; " " " /ES1:=/RAM*/FAS* ERR* CFE* ES1* ES0*/CAS*/ECK*/UDS + ;DETECTION - AFTER CAS /RAM*/FAS* ERR* CFE* ES1* ES0*/CAS*/ECK*/LDS + ; " /RAM*/FAS* ERR*/ES1* ECK ;EXTEND ONE CYCLE IF(VCC)/MS1 =/RAM*/FAS* ERR* CFE* ES1* ES0*/CAS*/ECK*/UDS + ;DETECTION - AFTER CAS /RAM*/FAS* ERR* CFE* ES1* ES0*/CAS*/ECK*/LDS + ; " /RAM*/FAS* ERR*/ES1* ECK ;EXTEND ONE CYCLE FUNCTION TABLE: CLK OE RAM CFE FAS ERR SEF DIR UDS LDS ECK ULE LLE CAS MS1 ES1 ES0 HLD ----------------------------- ;C RCF ES D UL E UL C MEE H ;LOAFA RE I DD C LL A SSS L ;KEMES RF R SS K EE S 110 D ;----------------------------INITIALIZE CHHXX XX X XX H ZZ Z XZZ Z ;1 ;-----------------------------RD WORD OR LOW BYTE (EDC MODE, CHK OFF) CLXLH HH H HH L HH H HHH H CLLLX HH H XX H HH H HHH H CLLLL HH H XL L HH L HHH H CLLLL HH H XL H HH L HHH H CLLLL HH H XL L LL H HHH H CLLLL HH H XL H LL H HHH H CLLLX HH H XX L LL H HHH H CLXLH HH H HH H HH H HHH H ;-----------------------------RD WORD OR HIGH BYTE (EDC MODE, CHK ON) CLXHH HH H HH L HH H HHH H ;10 CLXHX HH H XX H HH H HHH H CLLHL HH H LX L HH L LHH H CLLHL HH H LX H HH L HHH H CLLHL HH H LX L LL H HLH H CLLHL HH H LX H HH H LLL H CLLHX HH H XX L LL H HHL H CLXHH HH H HH H HH H HHH H CLXHH HH H HH L HH H HHH H ;-----------------------------RD WORD OR BYTE DMA (EDC MODE, CHK ON) CLXHX HH H XX H HH H HHH H ;20 CLLHL HH H LL L HH L LHH H CLLHL HH H LL H HH L HHH H CLLHL HH H LL L LL H HLH H CLLHL HH H LL H HH H LLL H CLLHL HH H LL L LL H HHL H CLLHL HH H LL H LL H HHL H CLLHL HH H LL L LL H HHH H CLLHL HH H LL H LL H HHH H CLLHX HH H XX L LL H HHH H CLXHH HH H HH H HH H HHH H ;30 CLXHH HH H HH L HH H HHH H ;-----------------------------RD WORD OR BYTE DMA - CORRECTION CYCLE CLLHX HH H XX H HH H HHH H CLLHL HH H XL L HH L LHH H CLLHL HH H XL H HH L HHH H CLLHL HH H XL L LL H HLH H CLLHL HH H XL H HH H LLL H CLLHL HL H XL L LL H HHL L CLLHL HL H XL H LL H HHL L CLLHL HH H XL L LL L HHL H CLLHL HH H XL H LL L HHL H ;40 CLLHL HH H XL L LL H HHH H CLLHL HH H XL H LL H HHH H CLLHX HH H XX L LL H HHH H CLXHH HH H HH H HH H HHH H ;-----------------------------RD - ACCESS ERROR CLXXH HH H HH L HH H HHH H CLLXX HH H XX H HH H HHH H CLLXL HH H LX L HH L HHH H CLLXL LX H LX H HH L HHH H CLLXL LX H LX L HH H HHH H CLLXL LX H LX H HH H HHH H ;50 CLLXX XX H XX L HH H HHH H CLXXH HH H HH H HH H HHH H ;-----------------------------WRITE WORD (ALL MODES) CPU CYCLE AFTER REFRESH CLXXH HH H HH L HH H HHH H CLLXL HH X XX H HH H HHH H CLLXL HH L LL L HH H HHL H CLLXL HH L LL H HH H HHL H CLLXL HH L LL L HH L HHL H CLLXL HH L LL H HH L HHL H CLLXX HH L XX L HH H HHH H CLLXH HH X HH H HH H HHH H ;60 CLXXH HH H HH L HH H HHH H ;----------------------------WRITE WORD (ALL MODES) DMA CYCLE CLLXX HH X HH H HH H HHH H CLLXL HH L HH L HH H HHL H CLLXL HH L HH H HH H HHL H CLLXL HH L HH L HH H HHL H CLLXL HH L XX H HH H HHL H CLLXL HH L LL L HH L HHL H CLLXL HH L LL H HH L HHL H CLLXL HH L LL L HH H HHH H CLLXL HH L LL H HH H HHH H ;70 CLLXX HH L XX L HH H HHL H CLXXH HH X HH H HH H HHH H CLXXH HH H HH L HH H HHH H ;-----------------------------WR BYTE (EDC MODE, CHK OFF) DMA STD CLLLX HH X HH H HH H HHH H CLLLL HH L HH L HH H HHL H CLLLL HH L HH H HH H HHL H CLLLL HH L HH L HH H HHL H CLLLL HH L HX H HH H HHL H CLLLL HH L HL L HH L HHH L CLLLL HH L HL H HH L HHH L ;80 CLLLL HH L HL L LH H HHH L CLLLL HH L HL H LH H HHH L CLLLL HH L HL L LH H HHL L CLLLL HH L HL H LH H HHL L CLLLL HH L HL L LH L HHL H CLLLL HH L HL H LH L HHL H CLLLL HH L HL L LH H HHH H CLLLL HH L HL H LH H HHH H CLLLX HH L HX L LH H HHH H CLXLH HH X HH H HH H HHH H ;90 ;-----------------------------WR BYTE (EDC MODE, CHK ON) CPU AFTER REFRESH CLLHH HH H HH L HH H HHH H CLLHX HH X XH H HH H HHH H CLLHL HH L LH L HH H HHL H CLLHL HH L LH H HH H HHL H CLLHL HH L LH L HH L LHH L CLLHL HH L LH H HH L HHH L CLLHL HH L LH L HL H HLH L CLLHL HX L LH H HH H LLL L CLLHL HX L LH L HL H HHL L CLLHL HH L LH H HL H HHL L ;100 CLLHL HH L LH L HL L HHL H CLLHL HH L LH H HL L HHL H CLLHX HH L XH L HL H HHH H CLXHH HH X HH H HH H HHH H ;-----------------------------ADDRESS ERROR CYCLE CLXXH HH H HH L HH H HHH H CLLXX HH X HH H HH H HHH H CLLXL HH L HH L HH H HHL H CLLXL HH L HH H HH H HHL H CLLXL HH L HH L HH H HHL H CLLXL HH L HH H HH H HHL H ;110 CLLXX HH L HH L HH H HHL H CLXXH HH X HH H HH H HHH H ;-----------------------------WRITE ACCESS ERROR CYCLE (WRITE PROTECTED) CLXXH HH H HH L HH H HHH H CLLXX HH X XX H HH H HHH H CLLXL HH L LX L HH H HHL H CLLXL HH L LX H HH H HHL H CLLXL LH L LX L HH H HHH H CLLXL LH L LX H HH H HHH H CLLXX LH L XX L HH H HHH H CLXXH HH X HH H HH H HHH H ;120 ------------------------------- DESCRIPTION: THIS DEVICE GENERATES CONTROL STROBES FOR MEMORY LATCHES, CAS AND WRITE STROBES FOR RAM MATRIX, HOLD SIGNAL FOR CPU CLOCK CONTROL AND STROBES FOR EDAC CHECK CIRCUITS. INPUT SIGNALS: ECK- EARLY CLOCK FAS- FORMATTED ADDRESS STROBE (ACTIVE LOW) SEF- SINGLE ERROR FLAG " " ERR- ACCESS ERROR (PROTECT OR PARITY) " " RAM- RAM CYCLE " " LDS- LOWER DATA STROBE " " UDS- UPPER " " " " DIR- DIRECTION TO MEMORY " " CFE- CHECK FUNCTION ON " HIGH OUTPUT SIGNALS: LLE- LOWER MEMORY LATCH ENABLE " LOW ULE- UPPER " " " " " ES0- EDAC S0 AND MEMORY WRITE STROBE " " CAS- MEMORY CAS STROBE " " HLD- HOLD CPU CLOCK " " ES1- EDAC S1 OR PARITY TEST STROBE " " MS1- " " " MIRROR " "