PAL16L8 PAT8035 **-1110-** MK,85-02-22 DS60 RAM DATA PATH CONTROL AT1 FAS ES1 LLE ULE ES0 DEF UDS LDS GND AT0 UDE LDE RAM DAS AEL DEL DIR BER VCC ;EQUATIONS: IF(VCC) /UDE = /RAM*/DAS*/FAS* DIR + /RAM* ES1*/ES0* ULE*/DIR IF(VCC) /LDE = /RAM*/DAS*/FAS* DIR + /RAM* ES1*/ES0* LLE*/DIR IF(VCC) /AEL = AT1*/FAS*/RAM*/DAS + /AT0*/DIR*/FAS*/RAM*/DAS IF(VCC) /DEL = /DEF*/RAM*/FAS*/DAS + /DEL*/RAM*/DAS IF(/RAM*/FAS) /BER = /AEL + /DEL FUNCTION TABLE: RAM DIR FAS DAS AT1 AT0 ES1 ES0 ULE LLE DEF UDE LDE AEL DEL BER ;R DFD AA EE UL D UL AD B ;A IAA TT SS LL E DD EE E ;M RSS 10 10 EE F EE LL R ---------------------------- H XXX XX XX XX X HH HH Z L XLH XX XX XX H HH HH H L HLL LX XX XX H LL HH H L HLL LX XX XX L LL HL L L HLL HX XX XX H LL LL L L HHL XX XX XX H HH HL Z L LLX LH XX LL H HH HH H L LLX LH LX HH H HH HH H L LLX LH HL LL H HH HH H L LLX LH HL HH H LL HH H L LLX LH HL HL H LH HH H L LLX LH HL LH H HL HH H L LLL LL HH HH H HH LH L ;10 L LLL LH HH XX L HH HL L ---------------------------- DESCRIPTION: THIS DEVICE CONTROLS DATA TRANSCEIVERS LOCATED BETWEEN CPU DATA BUS AND MEMORY DATA BUS. IT PERFORMS ACCESS PROTECTION AS WELL, GENERATING "BUS ERROR" SIGNAL ON PROHIBITED MEMORY ACCESSES. INPUT SIGNALS: FAS - FIXED ADDRESS STROBE (ACTIVE LOW) DAS - DELAYED " " " " ES0 - EDAC CONTROL S0 (INVERTED) ES1 - " " S1 ULE - UPPER MEMORY LATCH ENABLED " " LLE - LOWER " " " " " DEF - UNCORRECTABLE ERROR FLAG " " UDS - UPPER DATA STROBE (FROM CPU) " " LDS - LOWER " " " " " " DIR - DIRECTION TO MEMORY " " RAM - RAM CYCLE " " AT1 - ATTRIBUTE BIT 1 (EXISTING) " " AT0 - " " 0 (WRITE PROTECTED) " " OUTPUT SIGNALS: UDE - UPPER DATA ENABLE " " LDE - LOWER " " " " AEL - ACCESS ERROR LATCH " " DEL - DOUBBLE MEMORY ERROR LATCH " " BER - BUS ERROR " "