PAL16L8
PAT8031         **-1110-**          MK, 84-11-08
DS60 MAPPER CONTROL

FC2 A23 A22 A08 A07 DIR BGA CB6 CB7 GND
EAS PTE SWC PWC CXE TPT POE SOE STE VCC

EQUATIONS:

IF(VCC) /PTE = FC2* A23*/A22*/A08* A07* EAS* BGA         ;PAGE ACC.

IF(VCC) /SWC = FC2* A23*/A22*/A08*/A07* EAS*/DIR* BGA    ;SEGMENT WRITE

IF(VCC) /PWC = FC2* A23*/A22*/A08* A07* EAS*/DIR* BGA +  ;PAGE WRITE
              /CB6*/A23*/A22* EAS +                      ;RAM ACC
              /CB6* A23* A22*/A08* EAS                   ;I/O ACCESS

IF(VCC) /CXE =/FC2 +                                     ;USER
               FC2* EAS* A23                             ;SYS CTRL OR I/O

IF(VCC) /TPT = FC2*/A23*/A22* CB7* CB6 +                 ;RAM ACC LOW LEVEL
               FC2* A23* A22*/A08* CB7* CB6              ;I/O ACC  "    "

IF(VCC) /POE = FC2* A23*/A22*/A08* A07* EAS* DIR* BGA +  ;PAGE READ
              /CB6*/A23*/A22 +                           ;RAM ACCESS
              /CB6* A23* A22*/A08 +                      ;I/O   "
              /CB7* CB6*/A23*/A22 +                      ;RAM ACCESS - TEST
              /CB7* CB6* A23* A22*/A08                   ;I/O   "        "

IF(VCC) /SOE = FC2* A23*/A22*/A08*/A07* EAS* DIR* BGA +  ;SEGMENT READ
               FC2* A23*/A22*/A08* A07 +                 ;PAGE ACCESS
              /FC2 +                                     ;USER MODE
               FC2*/A23*/A22*/CB7 +                      ;RAM - RAM LEVEL
               FC2*/A23*/A22* CB7*/CB6 +                 ;RAM - HIGH BOOT
               FC2* A23* A22*/A08                        ;SYSTEM I/O

IF(VCC) /STE = FC2* A23*/A22*/A08*/A07* EAS* BGA         ;SYSTEM SEGMENT ACC


FUNCTION TABLE:

BGA CB7 CB6 FC2 A23 A22 A08 A07 DIR EAS
TPT CXE SOE POE PWC SWC STE PTE

;B CC F AA AA D E   T C S P P S S P
;G BB C 22 00 I A   P X O O W W T T
;A 76 2 32 87 R S   T E E E C C E E
------------------------------------
;BOOT LOW LEVEL
 X HH H LL XX X X   L H H H H H H H     ;1
 X HH H HH LX X H   L L L H H H H H
 X HH H LH XX X X   H X H H H H H H
 L XX X HL XX X X   X X X X H H H H
 H XX H HL LL L H   H L H H H L L H     ;5
 H XX H HL LL H H   H L L H H H L H
 H XX H HL LH L H   H L L H L H H L
 H XX H HL LH H H   H L L L H H H L
 H XX H HL LX X L   H H X X H H H H
;BOOT HIGH LEVEL
 X HL H LL XX X H   H H L L L H H H    ;10
 X HL H HH LX X H   H L L L L H H H
;RAM AND TEST LEVEL
 X LX X LL XX X H   H X L L L H H H
 X LX X HH LX X H   H X L L L H H H
 X LL L XX XX X H   H L L L L H H H
-----------------------------------

DESCRIPTION:

THIS DEVICE DECODES MAPPER ACCESSES AMONG COMMON
PROCESSOR ACTIVITY AND GENERATES APPROPRIATE
MAPPER CONTROLS.

INPUT SIGNALS:
FC2 - SYSTEM ACCESS                (ACTIVE HIGH)
AXX - ADDRESS BITS
DIR - TRANSFER TO MAPPER              "    LOW
BGA - DMA ACTIVITY                    "     "
CB6 - CONTROL BIT 6
CB7 -    "     "  7
EAS - EXTENDED ADDRESS STROBE         "    HIGH

OUTPUT SIGNALS:
PTE - PAGE TRANSCEIVER ENABLE         "    LOW
SWC - SEGMENT WRITE CMD               "     "
PWC - PAGE      "    "                "     "
CXE - CONTEX ENABLE                   "     "
TPT - TRANSPARENT PAGE TABLE          "     "
POE - PAGE OUTPUT ENABLE              "     "
SOE - SEGMENT OUTPUT ENABLE           "     "
STE - SEGMENT TRANSCEIVER ENABLE      "     "