DX-Forth Assembler 97-12-28 ------------------ Thå 8080/Z8° assembleò provideä witè DX-Fortè allowó thå useò tï write or compile forth 'code' words. Whilå DX-Fortè itselæ useó onlù 808° compatiblå code¬ thå assembleò ió capablå oæ assemblinç alì 808° oò Z8° instructions® Inteì mnemonicó arå useä foò thå 808° instructionó whilå thå Z80- onlù instructionó uså TDÌ (sometimeó referreä tï aó 'extendeä Intel'© mnemonics. Operands -------- Likå mosô fortè assemblers¬ thå operandó precedå thå instruction® Here are some examples: Zilog DX-Forth LD B,C C B MOV LD A,5 5 A MVI INC A A INR DEC (HL) M DCR INC (IX+9) 9 (X) INR INC (IY-6) -6 (Y) INR BIT 3,C C 3 BIT RES 2,(HL) M 2 RES SET 7,(IX-5) -5 (X) 7 SET Registers --------- Codå wordó maù uså anù cpõ registeró excepô foò thå BÃ register¬ whicè ió useä aó DX-Forth'ó IÐ oò interpretivå pointer® Iæ iô ió desireä tï uså thå BÃ registeò theî itó contentó shoulä bå saveä oî entrù tï thå codå worä anä restoreä beforå returninç tï forth. Local labels ------------ Thå DX-Fortè assembleò useó locaì labeló tï marë addresseó foò flo÷ control® Labeló arå assigneä anä referenceä aó follows: $: ( u -- ) Assigî thå addresó oæ thå nexô availablå                     dictionarù locatioî (HERE© tï labeì u $ ( u -- addr )   Returî thå addresó assigneä tï labeì u Uð tï 2° labeló (numbereä ± tï 20© maù bå useä withiî á codå definition® Thå assembleò wilì allo÷ labeló tï bå referenceä beforå theù havå beeî assigned® Á maximuí oæ 2µ such forwarä referenceó arå allowed. Thå followinç ió aî examplå oæ ho÷ tï codå thå fortè worä 0½ iî assembler® Iô useó onå labeì anä onå forwarä reference. Š CODE 0= ( n -- flag ) -1 H LXI \ load HL with -1 (true flag) D POP \ pop n to DE E A MOV D ORA \ test DE 1 $ JZ \ jump to label 1 if DE=0 H INX \ else increment HL (0=false flag) 1 $: \ define label 1 H PUSH \ push flag onto stack NEXT JMP \ return to forth END-CODE Executing High Level Forth -------------------------- Iô ió sometimeó convenienô tï executå high-leveì fortè wordó froí withiî á codå definition® Thå followinç twï utilitù wordó allo÷ this. C: ( -- ) Begiî thå executioî oæ high-leveì fortè wordó                     withiî á codå definition. ;C ( -- )          Enä thå executioî oæ high-leveì fortè wordó                     and resume execution of code instructions. Example - printing a message within a code definition CODE TEST ( -- ) C: \ begin high-level forth ." Hi There! " ;C \ end high-level forth NEXT JMP END-CODE Noteº onlù thå BÃ registeò contentó wilì bå automaticallù preserveä beforå thå higè leveì parô anä restoreä afterwards® Thå contentó oæ alì otheò 808° registeró wilì bå losô unlesó specificallù saved. Forth Addresses --------------- Thå followinç functionó returî importanô addresseó iî thå fortè system. NEXT ( -- adr ) Return the address of NEXT HPUSH ( -- adr ) Return the address of HPUSH DPUSH ( -- adr ) Return the address of DPUSH RPP ( -- adr ) Returî thå addresó oæ á pointeò tï thå                         return stack UP ( -- adr ) Returî thå addresó oæ á pointeò tï thå                         forth user area Mosô codå wordó enä witè á returî tï forth® Thió ió donå bù endinç thå codå worä witè á jumð tï NEXÔ - forth'ó addresó interpreter. HPUSÈ anä DPUSÈ arå speciaì entrieó tï NEXT® Á jumð tï HPUSÈ Špusheó thå HÌ registeò contentó tï thå stacë beforå enterinç NEXT® Á jumð tï DPUSÈ firsô pusheó thå DÅ registeò contentó anä theî thå HÌ contentó to the stack before entering NEXT. Error Checking -------------- Thå assembleò haó á minimuí oæ erroò checkinç anä iô ió possiblå tï compilå baä codå havinç incorrecô addressinç modeó oò operanä ordeò withouô anù warningó beinç given. Instruction Reference --------------------- Thå followinç listinç showó eacè Ziloç instructioî anä itó Intel/TDL equivalent in DX-Forth format. b bit position (0..7) d displacement added to IX or IY registers (-127..127) r register A,B,C,D,E,H or L n 8 bit operand (0..255) nn 16 bit operand (0..65535) Zilog Intel/TDL Zilog Intel/TDL ADC A,(HL) M ADC LD BC,(nn) nn LBCD ADC A,(IX+d) d (X) ADC LD BC,nn nn B LXI ADC A,(IY+d) d (Y) ADC LD DE,(nn) nn LDED ADC A,n n ACI LD DE,nn nn D LXI ADC A,r r ADC LD HL,(nn) nn LHLD ADC HL,BC B DADC LD HL,nn nn H LXI ADC HL,DE D DADC LD I,A STAI ADC HL,HL H DADC LD IX,(nn) nn LIXD ADC HL,SP SP DADC LD IX,nn nn X LXI ADD A,(HL) M ADD LD IY,(nn) nn LIYD ADD A,(IX+d) d (X) ADD LD IY,nn nn Y LXI ADD A,(IY+d) d (Y) ADD LD R,A STAR ADD A,n n ADI LD SP,(nn) nn LSPD ADD A,r r ADD LD SP,HL SPHL ADD HL,BC B DAD LD SP,IX SPIX ADD HL,DE D DAD LD SP,IY SPIY ADD HL,HL H DAD LD SP,nn nn SP LXI ADD HL,SP SP DAD LD r,(HL) r M MOV ADD IX,BC B DADX LD r,(IX+d) d (X) r MOV ADD IX,DE D DADX LD r,(IY+d) d (Y) r MOV ADD IX,IX X DADX LD r,n n r MVI ADD IX,SP SP DADX LD r,r' r' r MOV ADD IY,BC B DADY LDD LDD ADD IY,DE D DADY LDDR LDDR ADD IY,IY Y DADY LDI LDI ADD IY,SP SP DADY LDIR LDIR AND (HL) M ANA NEG NEG AND (IX+d) d (X) ANA NOP NOP AND (IY+d) d (Y) ANA OR (HL) M ORA AND n n ANI OR (IX+d) d (X) ORA AND r r ANA OR (IY+d) d (Y) ORA BIT b,(HL) M b BIT OR n n ORI ŠBIT b,(IX+d) d (X) b BIT OR r r ORA BIT b,(IY+d) d (Y) b BIT OTDR OUTDR BIT b,r r b BIT OTIR OUTIR CALL C,nn nn CC OUT (C),r r OUTP CALL M,nn nn CM OUT (n),A n OUT CALL NC,nn nn CNC OUTD OUTD CALL NZ,nn nn CNZ OUTI OUTI CALL P,nn nn CP POP AF PSW POP CALL PE,nn nn CPE POP BC B POP CALL PO,nn nn CPO POP DE D POP CALL Z,nn nn CZ POP HL H POP CALL nn nn CALL POP IX X POP CCF CMC POP IY Y POP CP (HL) M CMP PUSH AF PSW PUSH CP (IX+d) d (X) CMP PUSH BC B PUSH CP (IY+d) d (Y) CMP PUSH DE D PUSH CP n n CPI PUSH HL H PUSH CP r r CMP PUSH IX X PUSH CPD CCD PUSH IY Y PUSH CPDR CCDR RES b,(HL) M b RES CPI CCI RES b,(IX+d) d (X) b RES CPIR CCIR RES b,(IY+d) d (Y) b RES CPL CMA RES b,r r b RES DAA DAA RET RET DEC (HL) M DCR RET C RC DEC (IX+d) d (X) DCR RET M RM DEC (IY+d) d (Y) DCR RET NC RNC DEC BC B DCX RET NZ RNZ DEC DE D DCX RET P RP DEC HL H DCX RET PE RPE DEC IX X DCX RET PO RPO DEC IY Y DCX RET Z RZ DEC SP SP DCX RETI RETI DEC r r DCR RETN RETN DI DI RL (HL) M RALR DJNZ nn nn DJNZ RL (IX+d) d (X) RALR EI EI RL (IY+d) d (Y) RALR EX (SP),HL XTHL RL r r RALR EX (SP),IX XTIX RLA RAL EX (SP),IY XTIY RLC (HL) M RLCR EX AF,AF' EXAF RLC (IX+d) d (X) RLCR EX DE,HL XCHG RLC (IY+d) d (Y) RLCR EXX EXX RLC r r RLCR HALT HLT RLCA RLC IM 0 IM0 RLD RLD IM 1 IM1 RR (HL) M RARR IM 2 IM2 RR (IX+d) d (X) RARR IN A,(n) n IN RR (IY+d) d (Y) RARR IN r,(C) r INP RR r r RARR INC (HL) M INR RRA RAR INC (IX+d) d (X) INR RRC (HL) M RRCR INC (IY+d) d (Y) INR RRC (IX+d) d (X) RRCR INC BC B INX RRC (IY+d) d (Y) RRCR INC DE D INX RRC r r RRCR INC HL H INX RRCA RRC ŠINC IX X INX RRD RRD INC IY Y INX RST 0 0 RST INC SP SP INX RST 8h 1 RST INC r r INR RST 10h 2 RST IND IND RST 18h 3 RST INDR INDR RST 20h 4 RST INI INI RST 28h 5 RST INIR INIR RST 30h 6 RST JP (HL) PCHL RST 38h 7 RST JP (IX) PCIX SBC A,(HL) M SBB JP (IY) PCIY SBC A,(IX+d) d (X) SBB JP C,nn nn JC SBC A,(IY+d) d (Y) SBB JP M,nn nn JM SBC A,n n SBI JP NC,nn nn JNC SBC A,r r SBB JP NZ,nn nn JNZ SBC HL,BC B DSBC JP P,nn nn JP SBC HL,DE D DSBC JP PE,nn nn JPE SBC HL,HL H DSBC JP PO,nn nn JPO SBC HL,SP SP DSBC JP Z,nn nn JZ SCF STC JP nn nn JMP SET b,(HL) M SET JR C,nn nn JRC SET b,(IX+d) d (X) b SET JR NC,nn nn JRNC SET b,(IY+d) d (Y) b SET JR NZ,nn nn JRNZ SET b,r r b SET JR Z,nn nn JRZ SLA (HL) M SLAR JR nn nn JMPR SLA (IX+d) d (X) SLAR LD (BC),A B STAX SLA (IY+d) d (Y) SLAR LD (DE),A D STAX SLA r r SLAR LD (HL),n n M MVI SRA (HL) M SRAR LD (HL),r r M MOV SRA (IX+d) d (X) SRAR LD (IX+d),n n d (X) MVI SRA (IY+d) d (Y) SRAR LD (IX+d),r r d (X) MOV SRA r r SRAR LD (IY+d),n n d (Y) MVI SRL (HL) M SRLR LD (IY+d),r r d (Y) MOV SRL (IX+d) d (X) SRLR LD (nn),A nn STA SRL (IY+d) d (Y) SRLR LD (nn),BC nn SBCD SRL r r SRLR LD (nn),DE nn SDED SUB (HL) M SUB LD (nn),HL nn SHLD SUB (IX+d) d (X) SUB LD (nn),IX nn SIXD SUB (IY+d) d (Y) SUB LD (nn),IY nn SIYD SUB n n SUI LD (nn),SP nn SSPD SUB r r SUB LD A,(BC) B LDAX XOR (HL) M XRA LD A,(DE) D LDAX XOR (IX+d) d (X) XRA LD A,(nn) nn LDA XOR (IY+d) d (Y) XRA LD A,I LDAI XOR n n XRI LD A,R LDAR XOR r r XRA