;----------------------------------------------------------------
;      This module reads the I/O Bus Driven A-To-D card
;
; Written     By Richard Holmes        06-12-86
; Last Update By Richard Holmes        06-12-86
;----------------------------------------------------------------
;
	maclib	z80
	maclib	core
;
	public	ini$ad,rd$ad
	public	scan$ad
;
	extrn	cie,coe,cst,pdde,ptxt
	extrn	phde,crlf
;
;----------------------------------------------------------------
; 	---- A to D equates ----
;
; Note that all the signals are LOW going to that to generate the actual
; bit image ANDs and not or's must be used.
; 
cs$bar	equ	0000$1110b		; Chip select
rd$bar	equ	0000$1101b		; Read from ADC-1205
wr$bar	equ	0000$1011b		; Write to DC-1205
ss$bar	equ	0000$0101b		; Status from ADC-1205
;
; Setup what the bits mean
;
sars	equ	6			;bit 6 = Conversion in progress
byst	equ	2			;    2 = 0 for high byte, 1 for low
eoc	equ	1			;    1 = 1 for end of conversion
int	equ	0			;    0 = 1 for data ready to be read
;
; Setup the port addresses
;
data	equ	@gp3a			; General purpose port 3
cntl	equ	data + 1
mode	equ	data + 3		; 8255 mode
;
; 8255 modes of operation
;
rd$mod	equ	090h			; B = outputs, A = inputs
wr$mod	equ	080h			; B = outputs, A = outputs
;
;----------------------------------------------------------------
;    Initialize the A to D chip by disabling all its inputs
;
;----------------------------------------------------------------
;
ini$ad:
	mvi	a,rd$mod
	out	mode
	mvi	a,cs$bar and wr$bar and ss$bar	; Chip reset
	out	cntl
	mvi	a,0ffh
	out	cntl			; All inputs high = dead effectively
	ret
;
;----------------------------------------------------------------
;       Read the A-D channel. Return data in HL.
;
; On entry
;   A = channel
;
; On Exit
;  HL = data
;  All registers except A and HL preserved
;  A to D error sets HL to 
;                         FFFF for converter busy on entry
;                         FFFE for cannot begin conversion
;			  FFFD for cannot complete conversion
;----------------------------------------------------------------
;
rd$ad:
	push	d
	push	b
; Select read status mode
	mvi	a,rd$mod
	out	mode			; 8255 reading data port
;
; Status is on the data port now
;
	mvi	b,50			; Tries
wait$ready:
	mvi	a,cs$bar and ss$bar
	out	cntl			; Read status to see whats going on
	in	data
; 
	push	psw
	mvi	a,0ffh
	out	cntl
	pop	psw
;
	bit	sars,a			; Are we converting ?
	jrz	start$conversion
	djnz	wait$ready
	lxi	h,0ffffh		; Converter busy on entry
	jr	ioad$end
;
; Here we can start the conversion.
;
start$conversion:
	mvi	a,cs$bar and wr$bar	; Selects a write = start conversion
	out	cntl
	nop
	mvi	a,0ffh
	out	cntl			; Let it work a little
; A small delay and see if conversion started
	nop
	nop
	nop
	nop
	mvi	a,cs$bar and ss$bar	; Status read, SARS must be high
	out	cntl
	in	data			; Read the status now from the chip
; Save data, de-select A-D, restore data
	push	psw
	mvi	a,0ffh
	out	cntl			; Turn off the logic again;
	pop	psw
;
	bit	sars,a			; SARS high = converting
	jrnz	ad$started
	mvi	a,0fffeh		; Cannot start flag
	jr	ioad$end
;
; Here the A-D started. We wait a little the try to read the data
;
ad$started:
	mvi	b,35			; this is ~ 90uS
ad$wait:
	nop
	djnz	ad$wait
;
;Load a re-try counter now to get data back from converter
;
	mvi	b,20			; Retry counter to ensure conversion
ad$read:
	mvi	a,cs$bar and ss$bar	; Select a status read only
	out	cntl			; Read mode now, real quick
	in	data
; Save data, de-select A-D, restore data
	push	psw
	mvi	a,0ffh
	out	cntl			; Turn off the logic again;
	pop	psw
; Test for end of conversion.
	bit	int,a			; 1 = end of conversion, read the data
	jrnz	get$data
	djnz	ad$read
; Here, the converter timed out. Signal it.
	mvi	a,0fffdh
	jr	ioad$end
;
; Here, A = the status with end of conversion indicated.
; We now see if it is the high byte and if so, read data.
;
get$data:
	bit	byst,a
	jrz	get$data$high		; byst low = high byte in latches
; Here we got a low byte
	mvi	a,cs$bar and rd$bar
	out	cntl			; Read the first (high byte);
	nop
	mvi	a,0ffh
	out	cntl
	nop
;
get$data$high:
	lxi	d,0			; Compare
	mvi	b,10
;
; Loop here to get data and make sure stable
;
get$data$loop:
	mvi	a,cs$bar and rd$bar
	out	cntl			; Read the first (high byte);
	nop
	nop				; Allow cables to settle ?
	nop
	in	data			; Read chip
	ani	0001$1111b		; 12 bit A-D remember. 13th = sign
	mov	h,a
	mvi	a,0ffh
	out	cntl			; This clock second byte into latches
	nop
	nop
	mvi	a,cs$bar and rd$bar
	out	cntl			; Read the first (high byte);
	nop
	in	data			; Read chip
	mov	l,a
	mvi	a,0ffh
	out	cntl			; This clock second byte into latches
;
; See if data stable
;
	mov	a,l
	cmp	e			; L = E ?
	jrnz	not$same
	mov	a,h
	cmp	d
	jrz	ioad$end
;
not$same:
	xchg				; Hl -> DE looking for a match
	djnz	get$data$loop
	lxi	h,0
;
ioad$end:
	pop	b
	pop	d
	ret
;
;----------------------------------------------------------------
; Scan the A-D converter and display the values as they change.
; Indicate any error and any change in the error status.
;
; On Exit
;  All registers presumed lost
;----------------------------------------------------------------
;
scan$ad:
	call	ini$ad			; Initialize converter
	call	rd$ad
	jr	new$ad
;
; Now, read and display any changes.
; Exit when any key is pressed.
;
scan$loop:
	call	cst
	jnz	scan$end
	call	rd$ad			; Read converter
	lda	old$ad			; Compare to previous values
	cmp	l			; Same ?
	jrnz	new$ad
	lda	old$ad + 1
	cmp	h			; Same here = both the same. No change
	jrz	scan$loop
new$ad:
	shld	old$ad
	call	crlf
; Is it an Error ?
	mov	a,h
	cpi	0ffh			; Error flag
	jrz	ad$error
; Else display the value
	xchg
	call	pdde
	jmp	scan$loop
;
ad$error:
	xchg
	call	phde
	lxi	d,error0
; 
	mov	a,e			; E = the sub-code of the error
	cpi	0ffh			; Converter busy at start
	jrz	ad$msg
;
	lxi	d,error1
	cpi	0feh			; Cannot start conversion
	jrz	ad$msg
;
	lxi	d,error2
	cpi	0fdh
	jrz	ad$msg
; Else a silly error
	lxi	d,errorN
ad$msg:
	call	ptxt
	jmp	scan$loop
;
scan$end:
	call	cie
	ret
;
error0:	db	' Cannot start - Converter busy$'
error1:	db	' Cannot start - Converter wont start$'
error2:	db	' Cannot complete conversion - Stuck$'
errorN:	db	' Un-Recognized A-D error$'
;
; ---- Data ----
;
	dseg
old$ad	ds	2
;
; ------------------------------
; ----                      ----
; ---- End of program - Bye ----
; ----                      ----
; ------------------------------
;
	end
;
;