TITLE HDWINT - 'Hardware init and linking module' ; HDWINT performs the necessary system initialization. ; The SIO interrupt service routine entry points are ; also here so that the SIO data structure for the ; interrupting channel can be external to the SIO ; driver (HDLSIO). This allows that module to be ; generic. NOMACL EQU 1 ;Set non-zero to suppress listing ;of macro definitions INCLUDE RCONFIG.LIB INCLUDE STRUCT.LIB IF NOMACL .XLIST ENDIF SUBTTL 'Macro definitions' PAGE ; SIO data structure definition macro SDS MACRO CH LOCAL DSBEG CSEG DSBEG: DEFB CH ;Channel number DEFB DPORT&CH ;SIO data port DEFB CPORT&CH ;SIO control port DEFW NXTHO&CH ;NXTHO address DEFW ODONE&CH ;ODONE address DEFW NXTHI&CH ;NXTHI address REPT SDSLEN-($-DSBEG) DEFB 0 ENDM DSEG SDS&CH: DEFS SDSLEN ENDM ; External routine declaration macro ESUBS MACRO CH EXT NXTHO&CH,ODONE&CH,NXTHI&CH ENTRY XSKED&CH,CDS&CH ENDM ; Per-channel routine generation macro INTS MACRO CH XSKED&CH: LD IY,SDS&CH JP XSKED CDS&CH: LD IY,SDS&CH JP CDS I.TBE&CH: PUSH IY LD IY,SDS&CH JR TBE I.RBF&CH: PUSH IY LD IY,SDS&CH JP RBF I.EXT&CH: PUSH IY LD IY,SDS&CH JP EXT I.SRX&CH: PUSH IY LD IY,SDS&CH JP SRX ENDM ; HDLI call macro HDLINI MACRO CH LD IY,SDS&CH CALL HDLI ENDM SUBTTL 'External Linkages' PAGE .Z80 ENTRY HDWINT EXT HDLI,XSKED,CDS ;HDLSIO callable subs EXT I.TBE,I.RBF,I.EXT,I.SRX ;HDLSIO interrupt subs EXT RATES,TXDLYS EXT TICK X DEFL 0 REPT NUMCH ESUBS %X X DEFL X+1 ENDM .LIST SUBTTL 'Initialization Subroutine' PAGE ; Initialize the interrupt vector page HDWINT: LD HL,IPAGE ;Base of vectors LD DE,SPRINT ;Spurious handler LD B,128 ;Number of vectors ILOOP: LD (HL),E ;Set vector to SPRINT INC HL LD (HL),D INC HL DJNZ ILOOP ; Initialize the SIO vector register LD A,2 ;Set the SIO vector reg OUT (SIOBC),A LD A,0 OUT (SIOBC),A ; Initialize the timer CTC LD A,3 ;Reset the CTC channels OUT (CTC),A OUT (CTC+1),A OUT (CTC+2),A OUT (CTC+3),A LD A,10H ;Set the interrupt vector OUT (CTC),A LD A,CTCMOD ;Set up the timer CTC OUT (CTCCH),A LD A,CTCDIV OUT (CTCCH),A ; Initialize the baud rate generators LD A,(RATES) ;Get channel 0 speed OUT (0CH),A ;Set SIO B rate LD A,(RATES+2) ;Get channel 1 speed OUT (0),A ;Set SIO A rate PAGE ; Initialize the CPU interrupt logic and set the vectors LD A,IPAGE/256 ;Set the I register LD I,A IM 2 ;Interrupt mode 2 LD DE,IPAGE ;Set the vectors LD HL,IV LD BC,IVL LDIR ; Initialize the SIO data structures LD HL,SDSBAS ;Move initial data to RAM LD DE,SDS0 LD BC,SDSLEN*NUMCH LDIR ; Fill in the TXDLY values LD HL,SDS0+TXDLY ;Point to first TXDLY LD DE,TXDLYS ;Point to ROM values LD B,NUMCH ;Number of times to loop TXDLOP: LD A,(DE) ;Get low byte of value INC DE LD (HL),A ;Store in data structure INC HL LD A,(DE) ;Get high byte INC DE LD (HL),A ;Store PUSH DE LD DE,SDSLEN-1 ;Point to next data structure ADD HL,DE POP DE DJNZ TXDLOP ;Loop 'til done ; Initialize the SIO hardware X DEFL 0 REPT NUMCH HDLINI %X X DEFL X+1 ENDM RET SUBTTL 'Interrupt Service Routines' PAGE ; SPRINT - Spurious interrupt service ; A deadly condition requires a drastic cure. SPRINT: HALT ;Die, you old bastard ; SIO interrupt service entries X DEFL 0 REPT NUMCH INTS %X X DEFL X+1 ENDM TBE: PUSH HL LD HL,I.TBE JR SERVICE RBF: PUSH HL LD HL,I.RBF JR SERVICE EXT: PUSH HL LD HL,I.EXT JR SERVICE SRX: PUSH HL LD HL,I.SRX JR SERVICE SERVICE: PUSH PSW PUSH BC PUSH DE PUSH IX CALL VECTOR POP IX POP DE POP BC POP PSW POP HL POP IY EI RETI VECTOR: JP (HL) SUBTTL 'SIO Data Structures' PAGE SDSBAS EQU $ X DEFL 0 REPT NUMCH SDS %X X DEFL X+1 ENDM CSEG ; Interrupt vectors IV: DEFW I.TBE0,I.EXT0,I.RBF0,I.SRX0 DEFW I.TBE1,I.EXT1,I.RBF1,I.SRX1 REPT CTCCH-CTC DEFW SPRINT ENDM DEFW TICK IVL EQU $-IV END