I found the answers disk. So here goes:
Here are the answers to Commodore Trivia Edition #10 for September, 1994
Q $090) The 6502 has a rich history. It is modeled after another 8-bit
microprocessor. Name the processor.
A $090) The 65XX series of processors was modeled after the Motorola 6800.
Motorola hampered the design groups' efforts to pursue product
developments using the 6800. A core group of 8 designers left Motorola
and went to MOS Technologies, which was the largest producer of
calculator chips at the time. MOS decided it was time to go into
the CPU business.
Q $091) The 6502 has a older brother that was never produced. Name its
number designation and why it was not produced.
A $091) The older brother to the 6502 was the 6501. The 6501 was
pin-compatible with the 6800, which prompted a suit by Motorola.
Eventually, MOS reached an agreement where they scrapped the 6501
marketing, but were free to market the 6502.
Q $092) How many different opcodes are considered valid and "legal" on the
MOS NMOS 6502 line?
A $092) 151 opcodes are documented in the NMOS 6502 data book. The remaining
105 opcodes were not implemented, and exist as "don't care" states
in the opcode matrix. That means that some seemingly invalid
opcodes will actually perform pieces of two or more valid opcodes.
Newer CPU systems trap all non-implemented opcode usages, but not
the 6502.
Q $093) Every instruction takes at least __ cycles to complete. Fill in
the missing number.
A $093) 2. The architecture assumes that each opcode has two bytes in it and
one byte can be fetched per cycle. For instructions that use only
1 byte, the extra fetched byte (actually the next opcode), is thrown
away.
Q $094) Which instructions take more time than necessary as a result of the
answer to Q $093?
A $094) Although this is a subjective answer, One could nominate NOP on the
basis that NOP is generally believed to waste one execution cycle on
a particular processor, namely one cycle on the 65XX line. However,
one can argue that NOP simply means no operation, and has no ties to
length of execution. You be the judge.
All other instructions must take at least two cycles: one for opcode
fetch, one for operation.
Q $095) What did MOS Technologies manufacture befor introducing the 650X line
of microprocessors?
A $095) As stated above, it was calculator chips.
Q $096) Three companies manufactured the 6502 under a cross-licensing
agreement. Name them.
A $096) Rockwell, MOS Technologies, and Synertek.
Q $097) In NTSC-land, how fast does the 1MHz 6510 in the C64 actually run?
A $091) 1.022727143 MHz. It is derived by taking the main clock frequency
(14.31818MHz) and diving it by 14.
Q $098) What about in PAL-land?
A $091) 985,248.449 KHz. It is derived by taking the main clock frequency
(17.734472MHz) and dividing it by 18. Thus the PAL 64 actually runs
slower than the NTSC one.
Q $099) Data is latched into the 650X microprocessor on the (rising/falling)
edge?
A $091) Data is latched in to the 65XX on the falling edge of Phi0 (Phi1).
The timing diagram in some books (64 PRG is one) is incorrect.
Q $09A) Through the years, the 650X line has changed family numbers, yet
the part has not been changed. (A family number is the upper 2
digits in this case) Name the other family numbers used by MOS to
denote the 650X line.
A $091) the 75XX line used in the 264 series (Plus/4 and C16), and the 85XX
series used in the C64C and C128 series.
Q $09B) Consider the following code:
ldx #10
lda $ff,x
what location does the accumulator get loaded with?
A $091) Location $ff+0a = location $109
Q $09C) What about the following?
ldx #10
lda ($ff),x
A $091) This was a trick. The code is trying to use INDIRECT INDEXED indexing
mode using the x register, but that addressing mode can only be used
with the y register. If the code is changed to the following, legal
code:
ldx #10
lda ($ff),y
Then the following (mis)feature of the NMOS 65XX line shows up. One
would expect the base address would be loaded from $100:$0ff, but the
65XX designers decided not to bother with page boundary calculations
on this addressing method. The rule is: all addresses retrieved using
indirect addressing of any kind will ALWAYS be in zero-page. So,
the above code loads a base address from $ff and $00, then adds 10 to
it, then loads the value from that address.
Q $09D) How many CPU clock signal lines does the 650X require to run?
A $091) 1. The 6501 used two, as the 6800 used two, but the 6502 and
successors only required Phi0 (Phi1). Phi2 was generated on the CPU.
Q $09E) Where does the 650X line fetch its first byte from after reset?
A $091) $fffc. The address formed by reading $fffd and $fffc is stuffed into
the IP, and the code is read starting there. $fffc is read first,
since the 65XX line stores addresses in low byte, high byte format.
Q $09F) One of the original designers on the NMOS 6502 CPU now heads up
Western Design Center in Arizona, and makes the 65C02 and 65C816
CPU chips. Name him. Hint: it is not Chuck Peddle!
A $091) Bill Mensch. He hand-designed these newer parts in the 65XX line
in the same manner he and Chuck Peddle and others hand-designed the
6501 and 6502.
End of Commodore Trivia Edition #10!
Jim Brain
brain@mail.msen.com
2306 B Hartland Road
Hartland, MI 48353
(810) 737-7300 x8528
--
Jim Brain, Embedded Systems Designer, Brain Innovations.
brain@msen.com
Dabbling in VR, Old Commodore Computers, and Good Times!
"The above views DO reflect my employer, since I am my employer" - Jim Brain
--
Jim Brain, Embedded Systems Designer, Brain Innovations.
brain@msen.com
Dabbling in VR, Old Commodore Computers, and Good Times!
"The above views DO reflect my employer, since I am my employer" - Jim Brain
Jesper Nilsson // dat92jni@ludat.lth.se or jesper@df.lth.se