/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Keystone3 Quality of service endpoint definitions
 * Auto generated by K3 Resource Partitioning Tool
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#define PULSAR_UL_WKUP_0_CPU0_RMST	0x45D14000
#define PULSAR_UL_WKUP_0_CPU0_WMST	0x45D14400
#define PULSAR_UL_WKUP_0_CPU0_PMST	0x45D14800
#define PULSAR_UL_MAIN_0_CPU0_RMST	0x45D15000
#define PULSAR_UL_MAIN_0_CPU0_WMST	0x45D15400
#define PULSAR_UL_MAIN_0_CPU0_PMST	0x45D15800
#define PULSAR_ULS_MCU_0_CPU0_RMST	0x45D18000
#define PULSAR_ULS_MCU_0_CPU0_WMST	0x45D18400
#define PULSAR_ULS_MCU_0_CPU0_PMST	0x45D18800
#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R	0x45D20400
#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W	0x45D20800
#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW	0x45D21800
#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR	0x45D21C00
#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM	0x45D22000
#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM	0x45D22400
#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD	0x45D23000
#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR	0x45D23400
#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR	0x45D23800
#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD	0x45D23C00
#define USB3P0SS64_16FFC_MAIN_0_MSTR0	0x45D24800
#define USB3P0SS64_16FFC_MAIN_0_MSTW0	0x45D24C00
#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA	0x45D25400
#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W	0x45D25800
#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R	0x45D25C00
#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC	0x45D26800
#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC	0x45D26C00
#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC	0x45D27000
#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC	0x45D27400
#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC	0x45D27800
#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST	0x45D28000
#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD	0x45D29000
#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR	0x45D29400
#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC	0x45D29800
#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC	0x45D2A000
#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC	0x45D2C000
#define K3_DSS_UL_MAIN_0_VBUSM_DMA	0x45D30000
#define K3_DSS_UL_MAIN_1_VBUSM_DMA	0x45D30400
#define USB2SS_16FFC_MAIN_0_MSTR0	0x45D34000
#define USB2SS_16FFC_MAIN_0_MSTW0	0x45D34400
#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR	0x45D34800
#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD	0x45D34C00
#define USB2SS_16FFC_MAIN_1_MSTR0	0x45D35000
#define USB2SS_16FFC_MAIN_1_MSTW0	0x45D35400
