Scatter store quadwords
Scatter store of quadwords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled at the current Exception level.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rm | 0 | 0 | 1 | Pg | Zn | Zt |
if !HaveSVE2p1() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg);
<Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
<Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
constant integer VL = CurrentVL; constant integer PL = VL DIV 8; CheckNonStreamingSVEEnabled(); constant integer elements = VL DIV 128; bits(PL) mask = P[g, PL]; bits(VL) base; bits(64) offset; bits(VL) src; boolean contiguous = FALSE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, 128) then base = Z[n, VL]; offset = X[m, 64]; src = Z[t, VL]; for e = 0 to elements-1 if ElemP[mask, e, 128] == '1' then bits(64) addr = Elem[base, 2*e, 64] + offset; Mem[addr, 16, accdesc] = Elem[src, e, 128];
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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