SHA1H

SHA1 fixed rotate.

Advanced SIMD
(FEAT_SHA1)

313029282726252423222120191817161514131211109876543210
0101111000101000000010RnRd

SHA1H <Sd>, <Sn>

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;

Assembler Symbols

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(32) operand = V[n, 32]; // read element [0] only, [1-3] zeroed V[d, 32] = ROL(operand, 30);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.