Move two ZA tile slices to two vector registers
The instruction operates on two consecutive horizontal or vertical slices within a named ZA tile of the specified element size.
The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 2 in the range 0 to the number of elements in a 128-bit vector segment minus 2.
This instruction is unpredicated.
This is an alias of MOVA (tile to vector, two registers). This means:
It has encodings from 4 classes: 8-bit , 16-bit , 32-bit and 64-bit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | V | Rs | 0 | 0 | 0 | 0 | 0 | off3 | Zd | 0 | ||||||
size<1> | size<0> |
MOV { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offsf>:<offsl>]
is equivalent to
MOVA { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offsf>:<offsl>]
and is always the preferred disassembly.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | V | Rs | 0 | 0 | 0 | 0 | 0 | ZAn | off2 | Zd | 0 | |||||
size<1> | size<0> |
MOV { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offsf>:<offsl>]
is equivalent to
MOVA { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offsf>:<offsl>]
and is always the preferred disassembly.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | V | Rs | 0 | 0 | 0 | 0 | 0 | ZAn | o1 | Zd | 0 | |||||
size<1> | size<0> |
MOV { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offsf>:<offsl>]
is equivalent to
MOVA { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offsf>:<offsl>]
and is always the preferred disassembly.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | V | Rs | 0 | 0 | 0 | 0 | 0 | ZAn | Zd | 0 | ||||||
size<1> | size<0> |
MOV { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offsf>:<offsl>]
is equivalent to
MOVA { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offsf>:<offsl>]
and is always the preferred disassembly.
<Zd1> |
Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2. |
<Zd2> |
Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1. |
<HV> |
Is the horizontal or vertical slice indicator,
encoded in
|
<Ws> |
Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field. |
The description of MOVA (tile to vector, two registers) gives the operational pseudocode for this instruction.
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then when PSTATE.DIT is 1:
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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