Contiguous store words from vector (scalar index)
Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 4 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
It has encodings from 2 classes: SVE and SVE2
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1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | sz | Rm | 0 | 1 | 0 | Pg | Rn | Zt |
if !HaveSVE() && !HaveSME() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); constant integer esize = 32 << UInt(sz); constant integer msize = 32;
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1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | Rm | 0 | 1 | 0 | Pg | Rn | Zt |
if !HaveSVE2p1() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); constant integer esize = 128; constant integer msize = 32;
<Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<T> |
Is the size specifier,
encoded in
|
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g, PL]; bits(64) offset; bits(VL) src; constant integer mbytes = msize DIV 8; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; src = Z[t, VL]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(64) addr = base + (UInt(offset) + e) * mbytes; Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;
Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37
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