LD1B (scalar plus scalar, tile slice)

Contiguous load of bytes to 8-bit element ZA tile slice

The slice number within the tile is selected by the sum of the slice index register and immediate offset, modulo the number of 8-bit elements in a vector. The immediate offset is in the range 0 to 15. The memory address is generated by a 64-bit scalar base and an optional 64-bit scalar offset which is added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

SME
(FEAT_SME)

313029282726252423222120191817161514131211109876543210
11100000000RmVRsPgRn0off4
msz<1>msz<0>

LD1B { ZA0<HV>.B[<Ws>, <offs>] }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

if !HaveSME() then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt('0':Pg); integer s = UInt('011':Rs); integer t = 0; integer offset = UInt(off4); constant integer esize = 8; boolean vertical = V == '1';

Assembler Symbols

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V <HV>
0 H
1 V
<Ws>

Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs>

Is the slice index offset, in the range 0 to 15, encoded in the "off4" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer dim = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g, PL]; bits(64) moffs = X[m, 64]; bits(32) index = X[s, 32]; integer slice = (UInt(index) + offset) MOD dim; bits(VL) result; constant integer mbytes = esize DIV 8; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSME(MemOp_LOAD, nontemporal, contiguous, tagchecked); if n == 31 then if AnyActiveElement(mask, esize) || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; for e = 0 to dim - 1 addr = base + UInt(moffs) * mbytes; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = Mem[addr, mbytes, accdesc]; else Elem[result, e, esize] = Zeros(esize); moffs = moffs + 1; ZAslice[t, esize, vertical, slice, VL] = result;


Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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