UMOV

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (to general).

313029282726252423222120191817161514131211109876543210
0Q001110000imm5001111RnRd

32-bit (Q == 0)

UMOV <Wd>, <Vn>.<Ts>[<index>]

64-bit (Q == 1 && imm5 == x1000)

UMOV <Xd>, <Vn>.<Ts>[<index>]

integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer esize = 8 << size; constant integer datasize = 32 << UInt(Q); if datasize == 64 && esize < 64 then UNDEFINED; if datasize == 32 && esize >= 64 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ts>

For the 32-bit variant: is an element size specifier, encoded in imm5:

imm5 <Ts>
xx000 RESERVED
xxxx1 B
xxx10 H
xx100 S

For the 64-bit variant: is an element size specifier, encoded in imm5:

imm5 <Ts>
x0000 RESERVED
xxxx1 RESERVED
xxx10 RESERVED
xx100 RESERVED
x1000 D
<index>

For the 32-bit variant: is the element index encoded in imm5:

imm5 <index>
xx000 RESERVED
xxxx1 imm5<4:1>
xxx10 imm5<4:2>
xx100 imm5<4:3>

For the 64-bit variant: is the element index encoded in "imm5<4>".

Alias Conditions

AliasIs preferred when
MOV (to general)imm5 == 'x1000'
MOV (to general)imm5 == 'xx100'

Operation

if index == 0 then CheckFPEnabled64(); else CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n, idxdsize]; X[d, datasize] = ZeroExtend(Elem[operand, index, esize], datasize);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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