FCLAMP

Floating-point clamp to minimum/maximum number

Clamp each floating-point element in the destination vector to between the floating-point minimum value in the corresponding element of the first source vector and the floating-point maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the destination vector. If at least one element value contributing to a result is numeric and the others are either numeric or a quiet NaN, then the result is the numeric value. This instruction is unpredicated.

SVE2
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
01100100!= 001Zm001001ZnZd
size

FCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
01 H
10 S
11 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(VL) result; bits(VL) operand1 = Z[n, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) operand3 = Z[d, VL]; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; bits(esize) element2 = Elem[operand2, e, esize]; bits(esize) element3 = Elem[operand3, e, esize]; Elem[result, e, esize] = FPMinNum(FPMaxNum(element1, element3, FPCR[]), element2, FPCR[]); Z[d, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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