PMEVTYPER<n>

External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[31:0].

External register PMEVTYPER<n>_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[63:32] when FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_EXT64 is implemented.

External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMEVTYPER<n>_EL0 are RES0.

Attributes

Field descriptions

TC, bits [63:61]
When FEAT_PMUv3_TH is implemented, (FEAT_PMUv3_EDGE is not implemented or PMU.PMEVTYPER<n>_EL0.TE == 0) and (FEAT_PMUv3_TH2 is not implemented, or n is even or PMU.PMEVTYPER<n>_EL0.TLC IN {0b0x}):

Threshold Control. Defines the threshold function. In the description of this field:

V_B[n] is the value the event specified by PMEVTYPER<n>_EL0 would increment event counter n by on a processor cycle if the threshold function is disabled.
For odd values of n, V[n-1] is the value that event counter n-1 increments by on the same processor cycle. V[n-1] is the result of applying the threshold and edge functions on event counter n-1. If event counter n-1 is disabled then V[n-1] is zero. V[n-1] is not defined for even values of n.
TH[n] is the value of PMEVTYPER<n>_EL0.TH.

TC	Meaning
0b000	Not-equal. The counter increments by V_B[n] on each processor cycle when V_B[n] is not equal to TH[n].
0b001	Not-equal, count. The counter increments by 1 on each processor cycle when V_B[n] is not equal to TH[n].
0b010	Equals. The counter increments by V_B[n] on each processor cycle when V_B[n] is equal to TH[n].
0b011	Equals, count. The counter increments by 1 on each processor cycle when V_B[n] is equal to TH[n].
0b100	Greater-than-or-equal. The counter increments by V_B[n] on each processor cycle when V_B[n] is greater than or equal to TH[n].
0b101	Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when V_B[n] is greater than or equal to TH[n].
0b110	Less-than. The counter increments by V_B[n] on each processor cycle when V_B[n] is less than TH[n].
0b111	Less-than, count. The counter increments by 1 on each processor cycle when V_B[n] is less than TH[n].

Comparisons treat V_B[n] and TH[n] as unsigned integer values.

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC[2:1] is true:

If PMEVTYPER<n>_EL0.TC[0] is 0, then the counter increments by V_B[n].
If PMEVTYPER<n>_EL0.TC[0] is 1, then the counter increments by 1.

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC[2:1] is false:

If FEAT_PMUv3_TH2 is implemented, n is odd, and PMEVTYPER<n>_EL0.TLC is 0b01, then the counter increments by V[n-1].
Otherwise, the counter does not increment.

If PMEVTYPER<n>_EL0.{TC, TLC, TH} are zero then the threshold function is disabled.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

When FEAT_PMUv3_TH2 is implemented, PMU.PMEVTYPER<n>_EL0.TE == 0, n is odd and PMU.PMEVTYPER<n>_EL0.TLC == 0b10:

Threshold Control. Defines the threshold function. In the description of this field:

V_B[n] is the value the event specified by PMEVTYPER<n>_EL0 would increment event counter n by on a processor cycle if the threshold function is disabled.
V[n-1] is the value that event counter n-1 increments by on the same processor cycle. V[n-1] is the result of applying the threshold and edge functions on event counter n-1. If event counter n-1 is disabled then V[n-1] is zero.
TH[n] is the value of PMEVTYPER<n>_EL0.TH.

TC	Meaning
0b000	Not-equal. The counter increments by V[n-1] on each processor cycle when V_B[n] is not equal to TH[n].
0b010	Equals. The counter increments by V[n-1] on each processor cycle when V_B[n] is equal to TH[n].
0b100	Greater-than-or-equal. The counter increments by V[n-1] on each processor cycle when V_B[n] is greater than or equal to TH[n].
0b110	Less-than. The counter increments by V[n-1] on each processor cycle when V_B[n] is less than TH[n].

All other values are reserved.

Comparisons treat V_B[n] and TH[n] as unsigned integer values.

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is true, the counter increments by V[n-1].

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is false, the counter does not increment.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

When FEAT_PMUv3_EDGE is implemented and PMU.PMEVTYPER<n>_EL0.TE == 1:

Threshold Control. Defines the threshold function. In the description of this field:

V_B[n] is the value the event specified by PMEVTYPER<n>_EL0 would increment event counter n by on a processor cycle if the threshold function is disabled.
For odd values of n, V[n-1] is the value that event counter n-1 increments by on the same processor cycle. V[n-1] is the result of applying the threshold and edge functions on event counter n-1. If event counter n-1 is disabled then V[n-1] is zero. V[n-1] is not defined for even values of n.
TH[n] is the value of PMEVTYPER<n>_EL0.TH.

TC	Meaning
0b001	Equal to not-equal. The counter increments on each processor cycle when V_B[n] is not equal to TH[n] and V_B[n] was equal to TH[n] on the previous processor cycle.
0b010	Equal to/from not-equal. The counter increments on each processor cycle when either: V_B[n] is not equal to TH[n] and V_B[n] was equal to TH[n] on the previous processor cycle. V_B[n] is equal to TH[n] and V_B[n] was not equal to TH[n] on the previous processor cycle.
0b011	Not-equal to equal. The counter increments on each processor cycle when V_B[n] is equal to TH[n] and V_B[n] was not equal to TH[n] on the previous processor cycle.
0b101	Less-than to greater-than-or-equal. The counter increments on each processor cycle when V_B[n] is greater than or equal to TH[n] and V_B[n] was less than TH[n] on the previous processor cycle.
0b110	Less-than to/from greater-than-or-equal. The counter increments on each processor cycle when either: V_B[n] is greater than or equal to TH[n] and V_B[n] was less than TH[n] on the previous processor cycle. V_B[n] is less than TH[n] and V_B[n] was greater than or equal to TH[n] on the previous processor cycle.
0b111	Greater-than-or-equal to less-than. The counter increments on each processor cycle when V_B[n] is less than TH[n] and V_B[n] was greater than or equal to TH[n] on the previous processor cycle.

All other values are reserved.

Comparisons treat V_B[n] and TH[n] as unsigned integer values.

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is true:

If FEAT_PMUv3_TH2 is implemented, n is odd, and PMEVTYPER<n>_EL0.TLC is 0b10, then the counter increments by V[n-1].
Otherwise, the counter increments by 1.

On each processor cycle when the condition specified by PMEVTYPER<n>_EL0.TC is false, the counter does not increment.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TE, bit [60]
When FEAT_PMUv3_EDGE is implemented:

Threshold Edge. Enables the edge condition. When PMEVTYPER<n>_EL0.TE is 1, the event counter increments on cycles when the result of the threshold condition changes. See PMEVTYPER<n>_EL0.TC for more information.

TE	Meaning
0b0	Threshold edge condition disabled.
0b1	Threshold edge condition enabled.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [59]

SYNC, bit [58]
When FEAT_SEBEP is implemented:

Synchronous mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.

SYNC	Meaning
0b0	Asynchronous PMU exception is enabled.
0b1	Synchronous PMU exception is enabled.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

SVE mode filtering. Controls counting events in Streaming and Non-streaming SVE modes.

VS	Meaning
0b00	This mechanism has no effect on the filtering of events.
0b01	The PE does not count events in Streaming SVE mode.
0b10	The PE does not count events in Non-streaming SVE mode.

All other values are reserved.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TLC, bits [55:54]
When FEAT_PMUv3_TH2 is implemented and n is odd:

Threshold Linking Control. Extends PMEVTYPER<n>_EL0.TC with additional controls for event linking. See PMEVTYPER<n>_EL0.TC.

TLC	Meaning
0b00	Threshold linking disabled.
0b01	Threshold linking enabled. If the threshold condition described by PMEVTYPER<n>_EL0.TC is false, the counter increments by V[n-1]. Otherwise, the counter increments as described by PMEVTYPER<n>_EL0.TC.
0b10	Threshold linking enabled. If the threshold condition described by PMEVTYPER<n>_EL0.TC is true, the counter increments by V[n-1]. Otherwise, the counter does not increment.

All other values are reserved.

See PMEVTYPER<n>_EL0.TC for more information

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [53:44]

TH, bits [43:32]
When FEAT_PMUv3_TH is implemented:

Threshold value. Provides the unsigned value for the threshold function defined by PMEVTYPER<n>_EL0.TC.

If PMEVTYPER<n>_EL0.{TC, TH} are both zero and either FEAT_PMUv3_TH2 is not implemented or PMEVTYPER<n>_EL0.TLC is also zero, then the threshold function is disabled.

If PMU.PMMIR_EL1.THWIDTH is less than 12, then bits PMEVTYPER<n>_EL0.TH[11:UInt(PMU.PMMIR_EL1.THWIDTH)] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2^{UInt(PMU.PMMIR_EL1.THWIDTH)}.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

P, bit [31]

EL1 filtering. Controls counting events in EL1.

P	Meaning
0b0	This mechanism has no effect on filtering of events.
0b1	The PE does not count events in EL1.

If Secure and Non-secure states are implemented, then counting events in Non-secure EL1 is further controlled by PMEVTYPER<n>_EL0.NSK.

If FEAT_RME is implemented, then counting events in Realm EL1 is further controlled by PMEVTYPER<n>_EL0.RLK.

If EL3 is implemented, then counting events in EL3 is further controlled by PMEVTYPER<n>_EL0.M.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

U, bit [30]

EL0 filtering. Controls counting events in EL0.

U	Meaning
0b0	This mechanism has no effect on filtering of events.
0b1	The PE does not count events in EL0.

If Secure and Non-secure states are implemented, then counting events in Non-secure EL0 is further controlled by PMEVTYPER<n>_EL0.NSU.

If FEAT_RME is implemented, then counting events in Realm EL0 is further controlled by PMEVTYPER<n>_EL0.RLU.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

NSK, bit [29]
When EL3 is implemented:

Non-secure EL1 filtering. Controls counting events in Non-secure EL1. If PMEVTYPER<n>_EL0.NSK is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in Non-secure EL1. Otherwise, this mechanism has no effect on filtering of events in Non-secure EL1.

NSK	Meaning
0b0	When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Non-secure EL1.
0b1	When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Non-secure EL1. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

NSK

Meaning

0b0

When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Non-secure EL1.

0b1

When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Non-secure EL1.

When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSU, bit [28]
When EL3 is implemented:

Non-secure EL0 filtering. Controls counting events in Non-secure EL0. If PMEVTYPER<n>_EL0.NSU is not equal to PMEVTYPER<n>_EL0.U, then the PE does not count events in Non-secure EL0. Otherwise, this mechanism has no effect on filtering of events in Non-secure EL0.

NSU	Meaning
0b0	When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Non-secure EL0.
0b1	When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Non-secure EL0. When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events.

NSU

Meaning

0b0

When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Non-secure EL0.

0b1

When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Non-secure EL0.

When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSH, bit [27]
When EL2 is implemented:

EL2 filtering. Controls counting events in EL2.

NSH	Meaning
0b0	The PE does not count events in EL2.
0b1	This mechanism has no effect on filtering of events.

If EL3 is implemented and FEAT_SEL2 is implemented, then counting events in Secure EL2 is further controlled by PMEVTYPER<n>_EL0.SH.

If FEAT_RME is implemented, then counting events in Realm EL2 is further controlled by PMEVTYPER<n>_EL0.RLH.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

M, bit [26]
When EL3 is implemented and AArch64 is supported:

EL3 filtering. Controls counting events in EL3. If PMEVTYPER<n>_EL0.M is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in EL3. Otherwise, this mechanism has no effect on filtering of events in EL3.

M	Meaning
0b0	When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in EL3.
0b1	When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in EL3. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

Meaning

0b0

When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in EL3.

0b1

When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in EL3.

When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

MT, bit [25]
When FEAT_MTPMU is implemented or an IMPLEMENTATION DEFINED multi-threaded PMU extension is implemented:

Multithreading.

MT	Meaning
0b0	Count events only on controlling PE.
0b1	Count events from any PE with the same affinity at level 1 and above as this PE.

From Armv8.6, the IMPLEMENTATION DEFINED multi-threaded PMU extension is not permitted, meaning if FEAT_MTPMU is not implemented, this field is RES0. See ID_AA64DFR0_EL1.MTPMU.

This field is ignored by the PE and treated as zero when FEAT_MTPMU is implemented and disabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Secure EL2 filtering. Controls counting events in Secure EL2. If PMEVTYPER<n>_EL0.SH is equal to PMEVTYPER<n>_EL0.NSH, then the PE does not count events in Secure EL2. Otherwise, this mechanism has no effect on filtering of events in Secure EL2.

SH	Meaning
0b0	When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Secure EL2. When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events.
0b1	When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Secure EL2.

Meaning

0b0

When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Secure EL2.

When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events.

0b1

When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Secure EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When Secure EL2 is not implemented, access to this field is RES0 .

Otherwise:

T, bit [23]
When FEAT_TME is implemented:

Non-Transactional state filtering bit. Controls counting of events in Non-transactional state.

T	Meaning
0b0	This bit has no effect on the filtering of events.
0b1	Do not count Attributable events in Non-transactional state.

For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLK, bit [22]
When FEAT_RME is implemented:

Realm EL1 filtering. Controls counting events in Realm EL1. If PMEVTYPER<n>_EL0.RLK is not equal to PMEVTYPER<n>_EL0.P, then the PE does not count events in Realm EL1. Otherwise, this mechanism has no effect on filtering of events in Realm EL1.

RLK	Meaning
0b0	When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Realm EL1.
0b1	When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Realm EL1. When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

RLK

Meaning

0b0

When PMEVTYPER<n>_EL0.P == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.P == 1, the PE does not count events in Realm EL1.

0b1

When PMEVTYPER<n>_EL0.P == 0, the PE does not count events in Realm EL1.

When PMEVTYPER<n>_EL0.P == 1, this mechanism has no effect on filtering of events.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLU, bit [21]
When FEAT_RME is implemented:

Realm EL0 filtering. Controls counting events in Realm EL0. If PMEVTYPER<n>_EL0.RLU is not equal to PMEVTYPER<n>_EL0.U, then the PE does not count events in Realm EL0. Otherwise, this mechanism has no effect on filtering of events in Realm EL0.

RLU	Meaning
0b0	When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Realm EL0.
0b1	When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Realm EL0. When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events.

RLU

Meaning

0b0

When PMEVTYPER<n>_EL0.U == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.U == 1, the PE does not count events in Realm EL0.

0b1

When PMEVTYPER<n>_EL0.U == 0, the PE does not count events in Realm EL0.

When PMEVTYPER<n>_EL0.U == 1, this mechanism has no effect on filtering of events.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLH, bit [20]
When FEAT_RME is implemented:

Realm EL2 filtering. Controls counting events in Realm EL2. If PMEVTYPER<n>_EL0.RLH is equal to PMEVTYPER<n>_EL0.NSH, then the PE does not count events in Realm EL2. Otherwise, this mechanism has no effect on filtering of events in Realm EL2.

RLH	Meaning
0b0	When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Realm EL2. When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events.
0b1	When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events. When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Realm EL2.

RLH

Meaning

0b0

When PMEVTYPER<n>_EL0.NSH == 0, the PE does not count events in Realm EL2.

When PMEVTYPER<n>_EL0.NSH == 1, this mechanism has no effect on filtering of events.

0b1

When PMEVTYPER<n>_EL0.NSH == 0, this mechanism has no effect on filtering of events.

When PMEVTYPER<n>_EL0.NSH == 1, the PE does not count events in Realm EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [19:16]

evtCount[15:10], bits [15:10]
When FEAT_PMUv3p1 is implemented:

Extension to evtCount[9:0]. For more information, see evtCount[9:0].

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

evtCount[9:0], bits [9:0]

Event to count.

The event number of the event that is counted by event counter PMU.PMEVCNTR<n>_EL0.

The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.

If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.

Note

Arm recommends this behavior for all implementations of FEAT_PMUv3.

Otherwise, if PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:

For the range 0x0000 to 0x003F, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.
If FEAT_PMUv3p1 is implemented, for the range 0x4000 to 0x403F, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.
For other values, it is UNPREDICTABLE what event, if any, is counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is UNKNOWN.

Note

UNPREDICTABLE means the event must not expose privileged information.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMEVTYPER<n>_EL0

If FEAT_PMUv3_EXT32 is implemented and any of the following apply, then bits [63:32] of this register are accessible at offset 0xA00 + (4*n):

FEAT_PMUv3_TH is implemented.
FEAT_PMUv3p8 is implemented.
FEAT_PMUv3_SME is implemented.

Otherwise accesses at this offset are IMPLEMENTATION DEFINED.

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT64 is implemented

[63:0] Accessible at offset 0x400 + (8 * n) from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT32 is implemented

[31:0] Accessible at offset 0x400 + (4 * n) from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_SME is implemented)

[63:32] Accessible at offset 0xA00 + (4 * n) from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TC			TE	RES0	SYNC	VS		TLC		RES0										TH
P	U	NSK	NSU	NSH	M	MT	SH	T	RLK	RLU	RLH	RES0				evtCount[15:10]						evtCount[9:0]

PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 30

Purpose

Configuration

Attributes

Field descriptions

TC, bits [63:61]When FEAT_PMUv3_TH is implemented, (FEAT_PMUv3_EDGE is not implemented or PMU.PMEVTYPER<n>_EL0.TE == 0) and (FEAT_PMUv3_TH2 is not implemented, or n is even or PMU.PMEVTYPER<n>_EL0.TLC IN {0b0x}):

When FEAT_PMUv3_TH2 is implemented, PMU.PMEVTYPER<n>_EL0.TE == 0, n is odd and PMU.PMEVTYPER<n>_EL0.TLC == 0b10:

When FEAT_PMUv3_EDGE is implemented and PMU.PMEVTYPER<n>_EL0.TE == 1:

Otherwise:

TE, bit [60]When FEAT_PMUv3_EDGE is implemented:

Otherwise:

Bit [59]

SYNC, bit [58]When FEAT_SEBEP is implemented:

Otherwise:

VS, bits [57:56]When FEAT_PMUv3_SME is implemented:

Otherwise:

TLC, bits [55:54]When FEAT_PMUv3_TH2 is implemented and n is odd:

Otherwise:

Bits [53:44]

TH, bits [43:32]When FEAT_PMUv3_TH is implemented:

Otherwise:

P, bit [31]

U, bit [30]

NSK, bit [29]When EL3 is implemented:

Otherwise:

NSU, bit [28]When EL3 is implemented:

Otherwise:

NSH, bit [27]When EL2 is implemented:

Otherwise:

M, bit [26]When EL3 is implemented and AArch64 is supported:

Otherwise:

MT, bit [25]When FEAT_MTPMU is implemented or an IMPLEMENTATION DEFINED multi-threaded PMU extension is implemented:

Otherwise:

SH, bit [24]When EL3 is implemented and FEAT_SEL2 is implemented:

Otherwise:

T, bit [23]When FEAT_TME is implemented:

Otherwise:

RLK, bit [22]When FEAT_RME is implemented:

Otherwise:

RLU, bit [21]When FEAT_RME is implemented:

Otherwise:

RLH, bit [20]When FEAT_RME is implemented:

Otherwise:

Bits [19:16]

evtCount[15:10], bits [15:10]When FEAT_PMUv3p1 is implemented:

Otherwise:

evtCount[9:0], bits [9:0]

Accessing PMEVTYPER<n>_EL0

When FEAT_PMUv3_EXT64 is implemented

When FEAT_PMUv3_EXT32 is implemented

When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_SME is implemented)

TC, bits [63:61]
When FEAT_PMUv3_TH is implemented, (FEAT_PMUv3_EDGE is not implemented or PMU.PMEVTYPER<n>_EL0.TE == 0) and (FEAT_PMUv3_TH2 is not implemented, or n is even or PMU.PMEVTYPER<n>_EL0.TLC IN {0b0x}):

TE, bit [60]
When FEAT_PMUv3_EDGE is implemented:

SYNC, bit [58]
When FEAT_SEBEP is implemented:

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

TLC, bits [55:54]
When FEAT_PMUv3_TH2 is implemented and n is odd:

TH, bits [43:32]
When FEAT_PMUv3_TH is implemented:

NSK, bit [29]
When EL3 is implemented:

NSU, bit [28]
When EL3 is implemented:

NSH, bit [27]
When EL2 is implemented:

M, bit [26]
When EL3 is implemented and AArch64 is supported:

MT, bit [25]
When FEAT_MTPMU is implemented or an IMPLEMENTATION DEFINED multi-threaded PMU extension is implemented:

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

T, bit [23]
When FEAT_TME is implemented:

RLK, bit [22]
When FEAT_RME is implemented:

RLU, bit [21]
When FEAT_RME is implemented:

RLH, bit [20]
When FEAT_RME is implemented:

evtCount[15:10], bits [15:10]
When FEAT_PMUv3p1 is implemented: